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1、CMOS Analog IC DesignCMOS Analog IC DesignLecture 5 CMOScurrent sink and current mirrorMicro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC Designindex1.current sink / source1.1 simple current sink 1.2 cascode curr
2、ent sink 1.3 high-swing cascode current sink 1.4 self-biased cascode current sink 1.5 regulated cascode current sink 1.6 Widlar current source 1.7 peaking current source 1.8 Vt referenced current source 1.9 self-biasing Vt referenced current source 1.10 self-biasing gm referenced current source2.cur
3、rent mirror2.1 simple current mirror 2.2 cascode current mirror 2.3 large-output swing cascode current mirror 2.4 self-biased cascode current mirror 2.5 Wilson current mirror 2.6 regulated cascode current mirror 2.7 Sooch cascode current mirror 2.8 Sackinger current mirror 2.9 Gatti current mirror M
4、icro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSimple current sink 1.Characterization of current Sinks and Sources:2.A sink/source is characterized by two quantities:3. rout - a measure of the “flatness”
5、 of the current sink/source (its independence of voltage)4. VMIN - the minimum across the sink or source for which the current is no longer constantMicro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSimple
6、current sink(cont.)2.simple CMOS current sink:Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSimple current sink(cont.)It is important to note that the gate-source voltage consists of two parts as illus
7、trated below:VGS = VT0 + VON = Part to enhance the channel + Part to cause current flowNote : VMIN can be reduced by using large values of W/L.VON = VDS(sat) = VGS - VT0For the simple current sink:3. Gate-source voltage component:Micro-electronics Department Micro-electronics Department EIS Soochow
8、UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSimple current sink(cont.)4.increase rout of a current sink/source:Principle:In order to increase the output resistance, we may use negative series feedback because:rout (with feedback) = rout(without feedback) X 1 + Loop gai
9、n This is sometimes called “degeneration”.For an example:Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSimple current sink(cont.)How does it work?4.increase rout of a current sink/source (cont.):1.) As
10、sume iout increases.2.) As a result,vS increases.3.) Since the gate is held constant VGG, then vGS decreases.4.) The decrease in vGS causes iOUT to decrease opposing the original increase.Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Anal
11、og IC DesignCMOS Analog IC DesignCascode current sink1.basic circuit:vgs1 = vg2 = vb2 = 0; vout = (iout - gm2vgs2 - gmbs2vbs2)rds2 + rds1ioutvgs2 = 0 - vs2 = -ioutrds1vbs2 = 0 - vs2 = -ioutrds1vout = ioutrds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2rout =vout/iout= rds1 + rds2 + gm2rds1rds2 + gmbs2rds1r
12、ds2 gm2rds1rds2Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignCascode current sink(cont.)2. Gate-Source Matching Principle:Case one: If the VGS of two or more transistors are equal and the transistors a
13、re matched and operating in the saturation region, then the currents are related by the W/L ratios of the individual transistors. If VGS1 = VGS2, then Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignCasc
14、ode current sink(cont.)2. Gate-Source Matching Principle(cont.) :Case two: If the ID of two or more transistors are equal and the transistors are matched and operating in the saturation region, then the VGS are related by the W/L ratios ignoring bulk effects.If iD1 = iD2, thenIf (W/L)1=(W/L)2, then
15、VGS1 = VGS2Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignCascode current sink(cont.)3. Practical cascode current sink implementation: Does not require any batteries and uses the gate-source matching pr
16、inciple.VMIN is now equal to VT+V ON + VDS2(min) = VT + V ON + V ON = VT + 2V ONMicro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignHigh swing cascode current sink1.basic circuit:Since then if L/W is quadrup
17、led, then VON is doubled. VMIN = 2VON.But there is one problem:Because the VDS of the matching transistors, M1 and M3 are not equal, iOUT IREF.Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignHigh swing c
18、ascode current sink (cont.)2.improved high swing cascode current sink:To circumvent the problem iOUT IREF.the following current sink is utilized:Note that the drain-source voltage of M1 and M3 are identical causing iOUT to be a replication of IREF while Keeping VMIN=2VONBut there is another interest
19、ing Question:How does IREF flow into the M3-M5 combination of transistors since there is no path to the gate of M5? Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignHigh swing cascode current sink(cont.)3
20、.signal flow in transistors:1) As VDD increases (i.e. the circuit begins to operate), IREF cannot Flow into the drain of M5, so it flows through the path indicated by the arrow to the gate of M3. 2) It charges the stray capacitance and causes the gate-source voltage of M3 to increase to the exact va
21、lue necessary to cause IREF to flow through the M3-M5 combination.Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSelf-Biased Cascode Current Sink1.basic circuit:The VT + 2VON bias voltage can also be de
22、veloped through a series resistor.Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignRegulated cascode current sink1.basic circuit:Comments: 1)Achieves very high output resistance by increasing the loop gai
23、n due to the M4-M5 inverting amplifier.2) Allows M3 to maintain “constant” current even though it is no longer in the saturation region. Assume an iOUT increase vS3 increase vGS4 increase vG3 decrease Large decrease in vGS3 Large decrease in iOUTMicro-electronics Department Micro-electronics Departm
24、ent EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC Design Regulated cascode current sink (cont.)2. Calculate the output resistance:small signal model :Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog
25、IC DesignCMOS Analog IC DesignRegulated cascode current sink (cont.)3. 3. Calculate the VCalculate the VMINMIN: :Without the use of the VO1 battery shown, VMIN is pretty bad.It is,VMIN = VGS4 + VDS3(sat) = VT + 2VON If VO1 = VT , then VMIN = 2VON.This is accomplished by the following circuit:If VGS4
26、A - VGS4B = VDS2(sat) = VON,then VMIN = 2VON that is :Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignWidlar current sourceMicro-electronics Department Micro-electronics Department EIS Soochow University
27、EIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignPeaking current sourceFor M1 and M2 in strong inversion region: For M1 and M2 in weak inversion region:If M1=M2, thenMicro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC
28、DesignCMOS Analog IC DesignVt referenced current source Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSelf-biased Vt referenced current source Micro-electronics Department Micro-electronics Department
29、EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSelf-biasing gm referenced current sourceLet M3=M4 Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignCharacterization
30、of current mirrors 1. ideal characteristics of a current mirror: A current mirror is basically nothing more than a current amplifier. Output current linearly related to the input current, iout = Aiiin Input resistance is zero Output resistance is infinity In addition, the characteristic VMIN applies
31、 to both the output and the input. VMIN(in) is the range of input voltage over which the input resistance is not small VMIN(out) is the range of the output voltage over which the output resistance is not largeMicro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow
32、 University CMOS Analog IC DesignCMOS Analog IC DesignCharacterization of current mirrors(cont.)2.graphically :Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSimple current mirror1.basic circuit: Assume
33、 VDS2VGS-VT , thenMicro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSimple current mirror (cont.)1.basic circuit (cont.) : If the transistors are matched, then K1 = K2 and VT1 = VT2 to give,If vDS1 = vDS2,
34、 thenTherefore, the source of error are :1.) VDS1 VDS2 ; 2.) M1 and M2 are not matched.Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSimple current mirror(cont.)2.characteristics: Minimum output voltag
35、e is VMIN(out) = VON ; Output resistance is Rout =1/(ID) ; Input resistance is Rin 1/gm ;Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSimple current mirror(cont.)2.characteristics(cont.) : Current gai
36、n accuracy is poor Minimum input voltage is VMIN(in) = VT+VON VDS1 VDS2;It could be reduced to VON. output resistance can be enhanced Using cascoding techniqueMicro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC De
37、signCascode current mirror basic characteristics:Improve the output resistance by cascode topology: Rout rds2(gm4rds4); Rin rds3|(1/gm3) +rds1|(1/gm1) 2/gm ; VMIN(out) = VT + 2VON VMIN(in) = 2(VT +VON) Current gain: Excellent since vDS1 = vDS2 Micro-electronics Department Micro-electronics Departmen
38、t EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignLarge output swing cascode current mirrorBasic characteristics: Rout gm2rds2rds1Rin=(rds5+rds3+gm5rds5rds3)/gm3rds3(1+gm5rds5) 1/gm3 VMIN(out) = 2VON VMIN(in) = VT + VON Current gain is excellent because vDS1 =
39、vDS3.Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSelf-biased cascode current mirrorBasic characteristics: Rin 1/gm1+ R; Rout gm4rds4rds2 VMIN(in) = VT + 2VON VMIN(out) = 2VON Current gain matching is
40、 excellentMicro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignWilson current mirror Basic characteristics:Uses negative series feedback to achieve higher output resistance. Rout = rds3+rds2(1+gm3rds2+gm1rds1
41、gm3rds3)/(1 + gm2rds2) gm1rds1gm3rds3/gm2 Rin =(gm2 +gm3)/(gm1gm3) VMIN(in) = 2(VT+VON) VMIN(out) = VT + 2VON Current gain matching poor, vDS1 vDS2Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignRegulate
42、d cascode current mirror1. Evolution from the wilson current mirror:Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignRegulated cascode current mirror(cont.)2.basic characteristics: Rout (gm)2(rds)3 Rin 1/
43、gm4 VMIN(out) = VT+2VON (Can be reduced to 2VON) VMIN(in) = VT+VON (Can be reduced to VON) Current gain matching - good as long as vDS4 = vDS2Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSooch cascode
44、 current mirror1.basic circuit cell:MB must be in saturation region, while the MA is in triode region.Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSooch cascode current mirror(cont.)2. Basic character
45、istics:V1 = Vt + VonV2 = 2Vt + 3VonV3 = Vt + 2VonV4 = VonV5 = VonVout(min) = VDS1 + VDSAT 2 = 2Von VDD(min) = V2 = 2Vt + 3VonMicro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignSackinger current mirror Vout(
46、min) = VGS5 + VDSAT 1 = Von1 + Von5 + VtVDD(min) = VGS5 + VGS1 = Von1 + Von5 + 2Vt It may be necessary to add local compensation capacitors to the enhancement loops to prevent ringing during transients. The scheme can substantially slow down the settling times for large-signal transients.A typical s
47、ettling-time might be increased by 50%.Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC DesignGatti current mirror VGS5 = Von3 + Von7 + Vt VDS3 = Von3Vout(min) = VDS3 + VDSAT1 = Von1 + Von3VDD(min) = VGS5= Von3
48、 + Von7 + Vt If (W/L)1,2,3,4 = n (W/L)5,6,7,8,3A,4A, keep Iin nIB. M2 can be a fixed-bias cascode. The resulting circuit is less prone to instability.Micro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University CMOS Analog IC DesignCMOS Analog IC Designrefer
49、ences1.design of analog CMOS integrated circuits, Razavi .2.analysis and design of analog integrated circuits, P.R.Gray etc.3.“analog IC design” ，lectures by Shuenn-yuh Lee, EE/CCU , communication and biological integrated circuit lab.4. “analog IC design”, lectures by Jieh-Tsorng Wu , National Chiao-Tung University Department of Electronics EngineeringMicro-electronics Department Micro-electronics Department EIS Soochow UniversityEIS Soochow University
