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1、 1 信 息 工 程 学 院课 程 设 计 报 告题目：基于 FPGA 的智能电梯控制系统的实现Topic: INTELLIGENT ELEVATOR CONTROL SYSTEM二二 级级 学学 院院 信信 息息 工工 程程 学学 院院 专专 业业 班班 级级 通通 信信 工工 程程 2 2 班班 组组 员员 2014 年年 4 月月 25 日日ABSTRACT 2 Intelligent elevator compilation process is not easy. And I tried a variety of ways to realize the transfer of the
2、 state. At first I thought the affirmation is a finite state machine. But due to start I thought only six request (respectively for 1 6 / f) and then in teacher inspired and east ten on the second floor of the elevator actual operation situation I found, 6 button affirmation is not enough, so I adde
3、d five upward request button and five downward request button, so it has 16 button, because at that time I didnt think by signal and inverted method, so need analysis of true is too many, I also have no confidence. Nevertheless the problem are always to be solved, later I in our bedroom is a classma
4、te of reference books on saw a with VHDL language preparation intelligent elevator controller program, but is not complete, it gives me the greatest inspiration is “signal and inverted algorithm“, I discovered this way, then my workload is greatly reduced.I was not only use “signal and inverted algo
5、rithm“ outside, still adopted its “to the floor for elevator status transfer basis“ thought, it is really a good method, but I havent made any progress, one is it is with VHDL language preparation, and Im not very familiar with the language so not particularly understanding. KEY WORDS： A signal and
6、buy verilog CONTENTS 3 Chapter I SUMMARY.41.1 Introduction And Features of FPGA.41.2 VHDL Language And Procedures Outlined.51.2.1 VHDL Language Development.51.2.2 VHDL Language Features.6Chapter II ANALYSIS OF THE ELEVATOR CONTROL SYSTEM .72.1 Background Elevator Control.72.2 Specific Purpose And De
7、sign Of The Elevator Control Requirements .72.3 Elevator Controller Design Principles And Ideas.82.4 Elevator Control System State Diagram Analysis.10Chapter III DESIGN AND IMPLEMENTATION OF THE ELEVATOR CONTROL SYSTEM 133.1 VHDL Language Design And Simulation.133.1.1 Schematic Description Of Input
8、And Output Modules.133.1.2 Module Design Process.163.1.3 Waveform Simulation.183.2 Experimental Platform Elevator Control System To Achieve.24Chapter IV SCALABLE DESIGN .25END .27Chapter I SUMMARY 4 1.1 Introduction And Features Of FPGABackgroundCurrently circuit hardware description language (Veril
9、og or VHDL) completed, can be subjected to a simple synthesis and layout, fast burn to the FPGA for testing, the technology mainstream of modern IC design verification. These elements can be edited can be used to implement some basic logic gates (such as AND, OR, XOR, NOT) or more complex combinatio
10、nal functions such as decoders or mathematical equations. In most of the FPGAinside, these components can be edited in memory also includes elements such as flip-flops (Flip - flop) or other more complete memory blocks.FPGA WorksFPGA logic cell arrays using the LCA (Logic Cell Array) such a concept,
11、 including internal configurable logic block CLB (Configurable Logic Block),output input module IOB (Input Output Block) and internal connections (Interconnect) in three parts.The Basic Features Of The FPGA1) FPGA design using ASIC circuits (Application Specific Integrated Circuit), users do not nee
12、d to cast film production, you can get the combination of chips.2) FPGA specimen do other full-custom or semi-custom ASIC circuit. 5 3) FPGA internal triggers and rich I / O pin.4) FPGA circuits ASIC design cycle is the shortest, lowest development costs, one of the least risky devices.5) FPGA with
13、high-speed CHMOS technology, low power, compatible with CMOS, TTL level.It can be said, FPGA chip is small batch systems to improve system integration, one of the best reliability.1.2 VHDL Language And Procedures Outlined VHDL description of a digital system is mainly used for the structure, behavior, functions and interfaces. In addition to containing many statements with external hardware features, VHDL language forms and describe the style and syntax is very similar to the general high-level computer language. The program structur
