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1、2020/9/16,Jian Fang,1,集成电路工艺和版图设计概述Jian FangIC Design Center, UESTC,2020/9/16,Jian Fang,2,微电子制造工艺,2020/9/16,Jian Fang,3,IC常用术语,园片：硅片 芯片(Chip, Die)： 6、8 ：硅（园）片直径：1 25.4mm 6150mm; 8200mm; 12300mm; 亚微米1m的设计规范 深亚微米=0.5 m的设计规范 0.5 m 、 0.35 m 设计规范（最小特征尺寸） 布线层数：金属（掺杂多晶硅）连线的层数。 集成度：每个芯片上集成的晶体管数,2020/9/16,Ji
2、an Fang,4,IC工艺常用术语,净化级别：Class 1, Class 10, Class 10,000 每立方米空气中含灰尘的个数 去离子水 氧化 扩散 注入 光刻 .,2020/9/16,Jian Fang,5,生产工厂简介,PSI,2020/9/16,Jian Fang,6,Fab Two was completed January 2, 1996 and is a State of the Art facility. This 2,200 square foot facility was constructed using all the latest materials and
3、 technologies. In this set of cleanrooms we change the air 390 times per hour, if you do the math with ULPA filtration this is a Class One facility. We have had it tested and it does meet Class One parameters (without any people working in it). Since we are not making microprocessors here and we don
4、t want to wear space suits, we run it as a class 10 fab. Even though it consistently runs well below Class Ten.,2020/9/16,Jian Fang,7,Here in the Fab Two Photolithography area we see one of our 200mm .35 micron I-Line Steppers. this stepper can image and align both 6 & 8 inch wafers.,2020/9/16,Jian
5、Fang,8,Another view of one of the Fab Two Photolithography areas.,2020/9/16,Jian Fang,9,Here we see a technician loading 300mm wafers into the SemiTool. The wafers are in a 13 wafer Teflon cassette co-designed by Process Specialties and SemiTool in 1995. Again these are the worlds first 300mm wet pr
6、ocess cassettes (that can be spin rinse dried).,2020/9/16,Jian Fang,10,As we look in this window we see the Worlds First true 300mm production furnace. Our development and design of this tool began in 1992, it was installed in December of 1995 and became fully operational in January of 1996.,2020/9/
7、16,Jian Fang,11,Here we can see the loading of 300mm wafers onto the Paddle.,2020/9/16,Jian Fang,12,Process Specialties has developed the worlds first production 300mm Nitride system! We began processing 300mm LPCVD Silicon Nitride in May of 1997.,2020/9/16,Jian Fang,13,2,500 additional square feet
8、of State of the Art Class One Cleanroom is currently processing wafers! With increased 300mm & 200mm processing capabilities including more PVD Metalization, 300mm Wet processing / Cleaning capabilities and full wafer 300mm .35um Photolithography, all in a Class One enviroment.,2020/9/16,Jian Fang,1
9、4,Currently our PS300A and PS300B diffusion tools are capable of running both 200mm & 300mm wafers. We can even process the two sizes in the same furnace load without suffering any uniformity problems! (Thermal Oxide Only),2020/9/16,Jian Fang,15,Accuracy in metrology is never an issue at Process Spe
10、cialties. We use the most advanced robotic laser ellipsometers and other calibrated tools for precision thin film, resistivity, CD and step height measurement. Including our new Nanometrics 8300 full wafer 300mm thin film measurement and mapping tool. We also use outside laboratories and our excelle
11、nt working relationships with our Metrology tool customers, for additional correlation and calibration.,2020/9/16,Jian Fang,16,One of two SEM Labs located in our facility. In this one we are using a field emission tool for everything from looking at photoresist profiles and measuring CDs to double c
12、hecking metal deposition thicknesses. At the helm, another one of our process engineers you may have spoken with Mark Hinkle.,2020/9/16,Jian Fang,17,Here we are looking at the Incoming material disposition racks,2020/9/16,Jian Fang,18,Above you are looking at a couple of views of the facilities on t
13、he west side of Fab One. Here you can see one of our 18.5 Meg/Ohm DI water systems and one of four 10,000 CFM air systems feeding this fab (left picture), as well as one of our waste air scrubber units (right picture). Both are inside the building for easier maintenance, longer life and better contr
14、ol.,2020/9/16,Jian Fang,19,集成电路（Integrated Circuit, IC）：半导体IC，膜IC，混合IC 半导体IC：指用半导体工艺把电路中的有源器件、无源元件及互联布线等以相互不可分离的状态制作在半导体上，最后封装在一个管壳内，构成一个完整的、具有特定功能的电路。,半导体IC,双极IC,MOSIC,BiCMOS,PMOS IC,CMOS IC,NMOS IC,2020/9/16,Jian Fang,20,MOS IC及工艺,MOSFET Metal Oxide Semiconductor Field Effect Transistor . 金属氧化物半导体
15、场效应晶体管,Si,金属,氧化物（绝缘层、SiO2）,半导体,MOS(MIS)结构,2020/9/16,Jian Fang,21,栅氧化层厚度： 50埃1000埃（5nm100nm） VT阈值电压 电压控制,N沟MOS（NMOS）,P型衬底，受主杂质； 栅上加正电压，表面吸引电子，反型，电子通道； 漏加正电压，电子从源区经N沟道到达漏区，器件开通。,2020/9/16,Jian Fang,22,N衬底,p+,p+,漏,源,栅,栅氧化层,场氧化层,沟道,P沟MOS（PMOS）,VT,VGS,ID,+,-,VDS 0,N型衬底，施主杂质，电子导电； 栅上加负电压，表面吸引空穴，反型，空穴通道； 漏
16、加负电压，空穴从源区经P沟道到达漏区，器件开通。,2020/9/16,Jian Fang,23,CMOS,CMOS：Complementary Symmetry Metal Oxide Semiconductor 互补对称金属氧化物半导体特点：低功耗,VSS,VDD,Vo,Vi,CMOS倒相器,PMOS,NMOS,I/O,I/O,VDD,VSS,C,C,CMOS传输门,2020/9/16,Jian Fang,24,N-Si,P+,P+,n+,n+,P-阱,D,D,Vo,VG,VSS,S,S,VDD,CMOS倒相器截面图,CMOS倒相器版图,2020/9/16,Jian Fang,25,A NMOS Example,2020/9/16,Jian Fang,26,pwell,Pwell Active Poly N+ implant P+ implant Omicontact Metal,2020/9/16,Jian Fang,
