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1、第 1 讲认识集成电路设计及其设计过程认识集成电路设计及其设计过程认识集成电路设计及其设计过程认识集成电路设计及其设计过程CMOS数字集成电路数字集成电路(CMOS digital IC)IC的发展历史及现状(History of IC)IC 设计流程和方法(Design process and Methodology)IC 制造工艺技术(Fabrication process)IC EDA（CAD）工具使用(EDA tools)CMOS反相器设计反相器设计(CMOS Inverter)CMOS组合逻辑门设计组合逻辑门设计(Combinational Logic Circuit)CMOS时序逻
2、辑电路设计时序逻辑电路设计(Sequential Logic Circuit )IC 版图设计(Layout)IC 仿真技术(Simulation)存储器电路设计介绍(Memory Circuits)模拟IC设计介绍(Analog IC)课程性质：是一门专业基础课程课程性质：是一门专业基础课程主要介绍主要介绍CMOS数字集成电路设计的基础知识数字集成电路设计的基础知识共共40课时（课时（32理论课时理论课时+8实验课时）实验课时）完成完成4个实验个实验对准备从事对准备从事IC行业的学生来讲，本课程只是一行业的学生来讲，本课程只是一个基础，还需要继续深入学习更多关于个基础，还需要继续深入学习更多
3、关于IC设计设计的知识，如数字的知识，如数字IC深入，模拟深入，模拟IC，RF IC等。等。实验一（实验一（2学时）学时）反相器电路设计（Simulation and Layout）实验二（实验二（2学时）学时）NAND电路设计（Simulation and Layout）实验三（实验三（2学时）学时）AND 电路设计（Simulation and Layout）实验四（实验四（2学时）学时）D触发器电路设计（Simulation and Layout）完成一个完成一个4 4 SRAM芯片的设计芯片的设计3人一组人一组项目过程项目过程：A 期中期中Oral presentationB 期末期末
4、Oral presentationC 项目报告书一份项目报告书一份D 3人项目成绩相同人项目成绩相同课堂提问和作业课堂提问和作业10%实验实验20%考试考试 （开卷）（开卷）70%规则：规则：（1）1个问题和个问题和4次作业，每次次作业，每次/个个2分，共分，共10分；分；（2）每个实验完成得）每个实验完成得5分，共分，共20分；分； （3）点名）点名1次不到，次不到，10分没了；分没了； （4）抄作业，抄实验报告，相应分数没了；）抄作业，抄实验报告，相应分数没了；（5）请假规则：必须有正规请假手续和课前请假。）请假规则：必须有正规请假手续和课前请假。教材中文版周润德等译，数字集成电路设计透视
5、第二版，电子工业出版社(Jan M. Rabaey, et al. Digital Integrated Circuits, 2nd e, Prentice Hall, 2004)参考书Sung-Mo (Steve) Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis & Design, 3rd Edition, Mc Graw-Hill 2003R. Jacob Baker, CMOS Circuit Design, Layout, and simulation, 3rd Edition, Wiley, 2010韩
6、雁，集成电路设计CAD/EDA工具实用教程，机械工业出版社，2010模拟集成电路Razavi，模拟CMOS集成电路设计，清华大学出版社，2005通用参考书（Bible）威斯特，CMOS超大规模集成电路设计，第三版，中国电力出版社CMOS (complementary metal oxide semiconductor)IC (integrated circuit)VLSI (very large scale integrated)ULSI (ultra-large scale integrated)MOSFET (metal oxide semiconductor field effect t
7、ransistors)SPICE (simulation program with integrated circuit emphasis)为什么需要集成电路？与以前的集成电路设计相比，为什么现在的集成电路设计出现了不同以及现在的集成电路设计遇到了哪些新的挑战？未来，集成电路将如何发展？Integration reduces device size（减小尺寸）Laptop, iPod, mp3, cellphone, .Integration improves the design（提高性能）higher speed; lower power consuption;more reliable.
8、Integration reduces manufacturing cost（降低成本）BOM (Board of Materials) cost reducesMass IC production reduces costDesign, fab, applicationEducationSoftwareCommunication/NetworkingFab cost: $2-$3 billionDriving force of world economyLarge investment: fab, packaging, design, EDAPentium 4 “Northwood”55M
9、transistors / 2-2.5GHzL=0.13mGordon Moore Intel Founder“The number of transistors on a chip doubled every 18 to 24 months.”Electronics, April 19, 1965.Gordon MooreIntel Co-Founder and Chairmain EmeritusImage source: Intel Corporation Electronic system in cars.Electronic financial system: e-banking,e
10、-money, e-stock, RFID lablePersonal computing/entertainmentMedical electronic systems.Internet: routers, firewalls, servers, storagesElectronic library (Google, .)DVD R/W, HDTV, Interactive TVIn general, consumer electronicsetc .qComplexity: Multi-million transistors on a single chip (smaller size/f
11、aster speed)qMultiple and conflicting specifications for high performance (power/speed/throughput)qCompetition: Short design timeqDesign Tools: Multiple tools involved, Complex design flowAnalog BasebandDigital Baseband(DSP + MCU)PowerManagementSmall Signal RFPowerRF Layout designers Circuit designe
12、rs (Digital/Analog/RF) Architects Test/Verification engineers Fabrication engineers System designers (SoC) CAD tool programmers Embedded System developers Software programmersFirst transistorBell Labs, 1947J. Bardeen, W. Shockley, and W. Brattain (1956 Nobel prize Laureate)1819581958年年 J. KilbyJ. Ki
13、lby（TITI）研制成功第一个集成电路）研制成功第一个集成电路19591959年年 R. NoyceR. Noyce（FairchildFairchild）第一个利用平面工艺制）第一个利用平面工艺制成集成电路成集成电路The First Integrated Circuits Bipolar logic1960sECL 3-input GateMotorola 1966First commercial IC logic gates Fairchild 1960TTL 1962 into the 1990sECL 1974 into the 1980s2019702300 transistor
14、s1 MHz operation21Pentium 4 “Northwood” Commercial Production: Year 2001L=0.13m 6ML Cu Low-kFC-PGA2MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935CMOS 1960s, but plagued with manufacturing problems (used in watches due to their power limitations)PMOS in 1960s (calculators)
15、NMOS in 1970s (4004, 8080) for speedCMOS in 1980s preferred MOSFET technology because of power benefitsBiCMOS, Gallium-Arsenide, Silicon-GermaniumSOI, Copper-Low K, strained silicon, High-k gate oxide.Source: ISSCC 2003 G. Moore “No exponential is forever, but forever can be delayed”1.8 Ghz58 M118 m
16、m2Apple Power G5, the fastestPC in 2003, has dual PPC 970CPU MicroprocessorASIC (Application Specific IC)2728 Freq(HZ)TransistorsDie sizemm2Power DateServerIBM Power 4+1.7G180M267N/A2003Itanium 21.5G410M374130W2003IBM Power 5 2G276M 389 N/A 2004/2PCIBM Power PC970 1.8G58M11842W2003/6Pentium 43.2G55M
17、13182W2003/6AMD Athlon 642.2G105M19289W2003/9Pentium 4 (Prescott)3.4G125M112103W2004/2 Pentium 4 180 nm (2001) 1.7 G Hz 42 M transistors 217 mm2 Pentium 4 130 nm (2003) 3.2G Hz 55 M Transistors 131 mm2 Pentium 4 90 nm (2004) 3.4 Hz 125 M Transistors 112 mm2 Pentium on 65nm (2005/2006) 250 Million Pe
18、ntium on 45nm (2007) 400 to 500 Million (All use 0.13 um technology except Pentium 4 Prescott, which uses 90 nm tech)300mm wafer and Pentium 4 IC. Photos courtesy of Intel. “Microscopic Problems” Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation C
19、lock distribution. “Macroscopic Issues” Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP Availability systems on a chip (SoC) Predictability etc.95%工程的艺术vMay be part of larger product design.vMajor levels of abstraction:specification architecture logic design circuit design layout
20、 designFabless DesignHousesEDAToolsCompaniesDesignServiceCompaniesLibrary & IPProvidersDedicated IC Manufacturers (Foundry)Post:EDA: Electronic Design AutomationIP: silicon Intellectual PropertyIDM: Integrated Device ManufacturerIntegratedservicePackaging & Testing HousesFull Custom Design FlowCircu
21、it is created by composing a transistor netlistSPICE simulation is performed to verify the circuitKnown as “capture-and-simulate” paradigmLayout is mostly done manuallyPopular for high-performance microprocessors & memoriesCell-Based Synthesis FlowDesign is first described by Hardware Description La
22、nguage (e.g., Verilog and VHDL)Based on a cell library, netlist is created by synthesis toolsKnown as “describe-and-synthesize” paradigmLayout can be done through automatic toolsBlock Specification(Finite State Machine,Arithmetic Expression,Boolean Expression)Logic Design Gate-Level Netlist Transist
23、or NetlistTechnology MappingSPICE SimulationSPICEModelLayout Design LayoutLayoutRulesDesign Rule Checking (DRC)Layout vs. Schematic Check (LVS)Parasitic (or wiring) RC extractionPost-Layout SPICE SimulationCheck if SPEC is met ?If yes, done.Otherwise, go back to optimize the designFunctionalityOne-b
24、it binary full-adderTechnology1 mm n-well CMOS technologySpeedInput to output delay 5 ns Area 3000 mm2Power Dissipation exactly one of A, B,C is 1Technology mappingMany simple AND OR gates are merged into a complex gate (or a cell in the cell library)Transistor aspect ratiopMOS (W/L) is usually larg
25、er than nMOS (W/L), e.g., 2:1xyxyx = (AB+BC+CA)y = (A+B+C) x + ABC)Post-layout SPICE simulationincludes the “parasitic resistance & capacitance”is more accurate than the pre-layout simulation (pre-sim)Ratio of channel widths2:1Propagation time tPHL or tPLH as defined aboveLow-to-high propagation tim
26、e （传播延时）tPLH = 8.2 ns ! Got to go back to optimize the design !C (Carry_in)SumTransistor Sizingchanges the aspect ratios (W/L) of selected transistorsA larger aspect ratio may lead to a higher speedWire Sizing is also more recently proposedPropagation Delay 5 ns !A/DPLAI/OcompRAMMetal1ViaMetal2I/O P
27、adRandom logic(standardcell design)52Architecture designSystem-level integrationlayoutNo violationMemorymoduleFunctionalmodelTestbenchRTL coding & simulationRTL codeCell Librarysynthesis viewRTL-synthesis (Design Compiler)Netlistphysical viewPlace & Route (Apollo)LayoutviolationPost-Layout Timing Ch
28、eck (Design Time)SDFSDF: standard delay formatEach cell has equal heightIC service company provides cell library (for specific fab. com.): 500 1200 cellsDesign rule + Abutting ruleCell 1Cell 2Space/2DCCBACCDCDBBCCCCellMetal1Metal2FeedthroughGNDVDDCDABCell library未来的25年内，CMOS技术仍将保持其主流技术地位；System on C
29、hip (SOC), 系统芯片是发展趋势。Foundry国内国内Foundry台湾地区和境外台湾地区和境外炬力集成电路设计有限公司中星微电子有限公司上海杰得微电子有限公司大唐微电子技术有限公司圣邦微电子有限公司瑞芯微电子有限公司展讯通信（上海）有限公司安凯技术有限公司上海海尔集成电路有限公司北京华虹集成电路设计有限责任公司硅谷数模半导体有限公司中国华大集成电路设计集团有限公司华润矽威科技（上海）有限公司深圳艾科创新微电子有限公司智多微电子（上海）有限公司昂宝电子(上海)有限公司晶门科技（深圳）有限公司深圳致芯微电子有限公司深圳市力合微电子有限公司重庆西南集成电路设计有限公司北京思旺电子技术有限公司杭州友旺电子有限公司华亚微电子(上海)有限公司苏州华芯微电子有限公司 上海富瀚微电子有限公司 北京凌讯华业科技有限公司 绍兴芯谷科技有限公司 北京中科亿芯信息技术有限公司 杭州士兰微电子有限公司杭州国芯科技有限公司等等 刚才的发言，如刚才的发言，如有不当之处请多指有不当之处请多指正。谢谢大家！正。谢谢大家！69
