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1、Verilog_12864 module lcd (clk, rs, rw, en,dat); input clk; output 7:0 dat; output rs,rw,en; /tri en; reg e; reg 7:0 dat; reg rs; reg 15:0 counter; reg 5:0 current,next; reg clkr; reg 1:0 cnt; parameter set0=6h0; parameter set1=6h1; parameter set2=6h2; parameter set3=6h3; parameter set4=6h4; paramete
2、r set5=6h5; parameter set6=6h6; parameter dat0=6h7; parameter dat1=6h8; parameter dat2=6h9; parameter dat3=6hA; parameter dat4=6hB; parameter dat5=6hC; parameter dat6=6hD; parameter dat7=6hE; parameter dat8=6hF; parameter dat9=6h10; parameter dat10=6h12; parameter dat11=6h13; parameter dat12=6h14; p
3、arameter dat13=6h15; parameter dat14=6h16; parameter dat15=6h17; parameter dat16=6h18; parameter dat17=6h19; parameter dat18=6h1A; parameter dat19=6h1B; parameter dat20=6h1C; parameter dat21=6h1D; parameter dat22=6h1E; parameter dat23=6h1F; parameter dat24=6h20; parameter dat25=6h21; parameter dat26
4、=6h22; parameter dat27=6h23; parameter dat28=6h24; parameter nul=6hF1; always (posedge clk) begin counter=counter+1; if(counter=16h000f) clkr=clkr; end always (posedge clkr) begin current=next; case(current) set0: begin rs=0; dat=8h30; next=set1; end /*设置8位格式, set1: begin rs=0; dat=8h0C; next=set2;
5、end /*整体显示,关光标,不闪烁*/ set2: begin rs=0; dat=8h6; next=set3; end /*设定输入方式,增量不移位*/ set3: begin rs=0; dat=8h1; next=dat0; end /*清除显示*/ dat0: begin rs=1; dat=8hc9; next=dat1; end /显示第一行 dat1: begin rs=1; dat=8hee; next=dat2; end dat2: begin rs=1; dat=8hdb; next=dat3; end dat3: begin rs=1; dat=8hda;next=d
6、at4; end dat4: begin rs=1; dat=8hca; next=dat5; end dat5: begin rs=1; dat=8hd0; next=dat6; end dat6: begin rs=1; dat=2; next=dat7; end dat7: begin rs=1; dat=1;next=dat8; end dat8: begin rs=1; dat=E; next=dat9; end dat9: begin rs=1; dat=D;next= dat10 ; end dat10: begin rs=1; dat=8hB5; next=dat11; end
7、 dat11: begin rs=1; dat=8hE7; next=dat12; end dat12: begin rs=1; dat=8hd7;next=dat13; end dat13: begin rs=1; dat=8hd3; next=set4; end set4: begin rs=0; dat=8h90; next=dat14; end /显示第二行 dat14: begin rs=1; dat=N; next=dat15; end dat15: begin rs=1; dat=I; next=dat16; end dat16: begin rs=1; dat=O; next=
8、dat17; end dat17: begin rs=1; dat=S; next=dat18; end dat18: begin rs=1; dat= ; next=set5; end dat19: begin rs=1; dat=I; next=dat20; end dat20: begin rs=1; dat=I; next=set5; end set5: begin rs=0; dat=8h88; next=dat21; end /显示第三行 dat21: begin rs=1; dat=F; next=dat22; end dat22: begin rs=1; dat=P; next
9、=dat23 ; end dat23: begin rs=1; dat=G; next=dat24; end dat24: begin rs=1; dat=A; next=set6; end set6: begin rs=0; dat=8h98; next=dat25; end /显示第四行 dat25: begin rs=1; dat=S; next=dat26; end dat26: begin rs=1; dat=O; next=dat27; end dat27: begin rs=1; dat=P; next=dat28; end dat28: begin rs=1; dat=C; n
10、ext=nul; end nul: begin rs=0; dat=8h00; / 把液晶的E 脚 拉高 if(cnt!=2h2) begin e=0;next=set0;cnt=cnt+1; end else begin next=nul; e=1; end end default: next=set0; endcase end assign en=clkr|e; assign rw=0; endmodule verilog写的LCD1602显示/ LCD_Top.v/连接Clock_Gen模块和LCD_Driver模块module LCD_Top(clk_48M,rst,LCD_EN,RS
11、,RW,DB8);input clk_48M,rst;output LCD_EN,RS,RW;output 7:0 DB8;wire clk_LCD; /用于将Clock_Gen模块clk_LCD输出连接至LCD_Driver模块的clk_LCD输入Clock_Gen U1(.clk_48M(clk_48M), .rst(rst), .clk_LCD(clk_LCD);LCD_Driver U2(.clk_LCD(clk_LCD), .rst(rst), .LCD_EN(LCD_EN), .RS(RS), .RW(RW), .DB8(DB8); endmodule/ Clock_Gen.v/*为LCD_Drvier模块产生500Hz的时钟信号*/module Clock_Gen(clk_48M,rst,clk_LCD);input clk_48M,rst; /rst为全局复位信号（高电平有效） output clk_LCD; wire clk_counter;reg 11:0 cnt; /对时钟进行计数分频wire clk_equ;reg 9:0 count;reg clk_BUF;parameter counter= 50; /多少分频/* 模块名称：分频器* 功能描述：通过计数器实现分频功能.*
