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1、1,WAT Parameters Review,Speaker: Alan Huang,2,Flow,Why WAT? WAT Parameter Review. Process test Methodology. Device test Methodology. Process Factor Influence on WAT Para. WAT Application General Guide-line when WAT fail Example introduce,3,Why WAT?,Debug the Process Error. Monitor Process Window. Ch
2、eck Design Rule. Control the Process Parameters(SPC). Reliability Characterization. Device Modeling for Circuit Design. Develop next Generation.,4,Test site and Test line location,5,Device Categorization,Active Device MOSFET(N/P),Field Transistor,BJT,Diode Passive Device Resistor,Capacitors Design r
3、ules Isolation,lines(Spacing,Continuity) contact,extension,Resistor Diffusion regions N+,N-,P+,N-Well,P-Well,Deep-NW Thin films P1,P2,M1,M2,M3 Contact: C3 to N+/P+,Via C3 to P1,P2,6,WAT Parameter Review,Process Part: Spacing (Bridge,short) Continuity (Open) Isolation Sheet Rs Contact Rc Kelvin Struc
4、ture for Resistance Integrity (Inter layer dielectric) Extension rule check CD measurement Junction leakage,Device Part: Gm (Vth,Current Gain) Idsat (Asym) Ioff Swing Gamma factor BKV Isub Leff,Rext,Weff Field Device test Capacitance,7,Process Part:,(1) Spacing (Bridge,short) Define：验证在Process中，同层/同
5、层之间的隔绝能力! Measurement method： Force 1uA电流到导线上，假若线路中有short，则测量出的电压值就偏低(7volt.需注 意此 Structure之 bottom layer可垫其它layers, 以模拟不同topography下Photo.&Etching 的能力！,Pad1,Pad2,Spacing:(P1,P2,M1,M2,M3),Width:(P1,P2,M1,M2,M3),8,Process Part:,(2) Continuity (Open) Continuity 的值可反映出Metal,Poly 1 or Poly 2 CD 的控制能力！一般
6、来说，此项参数 要与Spacing要同时来看，如此才能判定 Layer的status是否正常！,Pad1,Pad2,Spacing:(P1,P2,M1,M2,M3),Width:(P1,P2,M1,M2,M3),9,Process Part:,(3) Isolation Define：验证在 Process中，两不同层之间的隔绝能力！ PS：此Pattern要注意,若oxidation quality 太差,亦会影响到P1/C3是否short的误判 Isolation example：P1/C3, P2/C3, P1/P2, M1/M2,PAA,C3,M1,Poly1,PAA外框P+IM,P-
7、IM,NW外框PFIM,10,Process Part:,(4)Sheet（薄层电阻 Rs） Define：因厚度测量不易，故Define之 =1/=nq R=V/I=(L/WT)=(/T)x(L/W) Rs= /T=Rx(W/L) PS：(Conductivity 传导系数)；(Resistivity 电阻率)； (mobility 迁移率)； n(concentration 浓度)；T(thickness 厚度)；,NAA,PW,C3,NAA,M1,C3,M1,Poly2,N+IMP,N-IMP,PW,Poly1,11,Process Part:,(5) Contact（接触电阻）Rc D
8、efine：利用Chain的结构,将contact的阻值以Pattern design的方式模拟出实际的 contact Rc大小！ PS：(1) Rc Normalize 后的大小，往往会失真，故当个数过多时，不建议Normalize！ (2) 以pattern design而言,有垫其它layer（如右下) 的Structure在CMP的process 中已失去参考价值了！,M2,M2,M1,Via,M2,M2,0.465,1.25,1.15,M2,P1P2,M2,12,Process Part:,(6) Kelvin Structure for Resistance Define：以Fo
9、rce Current then Sense Voltage drop的方式,测量低阻值的导线或Contact 的四端电阻测量法！ PS：一般来说在Req50的结构中, Force I=0.01uA and Voltage lim=10V!(Req=L/W),Pad1,Pad2,Pad3,Pad4,1um,15um,70um,2um(W),70um,1000,L,13,Process Part:,(7) Integrity(Gate-Oxide-Integrity) Define:验证Gate oxide 的Quality 好坏之一项参数当Gate oxide uniformity不均,或In
10、terface间有defects时,会形成一漏电流路径失去Oxide Isolation的能力！ Measurement method: 一般测量法不外乎Force V/I and measure I/V 1. Force V and measure I: Sweep Volt on Poly gate,and Vb=ground then measure Ig(aboutpA),If Ig increase to 1uA,this Sweep Volt is BKV(normal large 7 V) 2. Force I and measure V: Force 1uA on Poly g
11、ate then measure Voltage PS:测量方式取决于Pattern design (common pad issue),WELL,Poly Gate,14,Process Part:,(8) Extension rule check Define：以sense漏电流的方式，测量Contact overlay 的Design rule check! PS：(1) 一般来说，layout 的结构会采用十字架的形式，最大的好处是在把shot issues 的问题抓出! (2) miss-align 与contact number无关！,M2,Via,M1,M1 ext to via
12、,用Poly4垫,15,Process Part:,(9) CD measurement Define: 籍由测量两条同长度，不同宽度的电阻，换算出其宽度CD大小！ PS: 当W=W1时 可测量得电阻R1 W=W2时 可测量得电阻R2 R1=Rs*L/(W1-W) R2=Rs*L/(W2- W) R1/R2=(W2- W) /(W1-W) 则W(CD loss),Rs皆可求得！ (P1 CD 大小影响到Channel length的长短,需特别注意）,16,Process Part:,(10) Junction leakage Define：一般来说leakage指的是反向偏压时的漏电流测量，
13、通常有以下三种分类： 1.Contact leak 2.Dielectric leak (usually for DRAM)3.Junction leak (bulk or peri) PS: I-bulk(meas)=A-bulk*J-area(current/um2)+L-peri*J-peri(current/um) I-finger(meas)=A-fing*J-area(current/um2)+L-peri(current/um) (J-area,J-peri 可求）,PW拉出,NAA有打Blanket N+imp,N-imp,C3,M1,17,Device Part:,Gm (V
14、th,Current Gain) Define:Gm=(Id/ Vg) Linear: Id=1/2(CoxW/L)(2(Vgs-Vt)Vds-Vds2) Gm= CoxW/L Saturation: Id=1/2(CoxW/L)(Vgs-Vt)2 Gm= CoxW/L(Vgs-Vt) Pinch-Off:Vds=Vgs-Vt Gm= Cox(W/L)Vds = Cox(W/L) PS:If value abnormal,It may have Gox, Leff or implant issues. Vth Measure method: Step1:Vds=0.1 Vs=Vb=0 and
15、swoop Vg Step2:Plot Ids Vgs and Gm Vgs curves Step3:find Gm(max),plot slop of this point on Ids Vgs From Linear function set Id=0then Vth=Vgs-V,0,3,Vg,Id,18,Device Part:,Idsat (Asym) Define: Idsat=Ids at Vgs=Vds=Vcc Ids Measure method: Step1:Vs=Vb=0,Vd=Vcc and Sweep Vg Step2:Plot Ids Vgs Step3:Find Ids at Vg=Vd=Vcc Ids Asymmetry check: Step1:Following the Ids measurement. Step2:Change Drain and Source Pin-assign,then measure Ids. Step3:Asym=ABS(Ids-Ids)/I
