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1、MOTOROLA CMOS LOGIC DATA 1 MC14553B ? ? ? The MC14553B 3digit BCD counter consists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing on
2、e BCD number or digit at a time. Digit select outputs provide display control. All outputs are TTL compatible. An onchip oscillator provides the lowfrequency scanning clock which drives the multiplexer output selector. This device is used in instrumentation counters, clock displays, digital panel me
3、ters, and as a building block for general logic applications. TTL Compatible Outputs OnChip Oscillator Cascadable Clock Disable Input Pulse Shaping Permits Very Slow Rise Times on Input Clock Output Latches Master Reset MAXIMUM RATINGS* (Voltages Referenced to VSS) SymbolParameterValueUnit VDDDC Sup
4、ply Voltage 0.5 to + 18.0V Vin, VoutInput or Output Voltage (DC or Transient) 0.5 to VDD + 0.5V IinInput Current (DC or Transient), per Pin 10mA IoutOutput Current (DC or Transient), per Pin+ 20mA PDPower Dissipation, per Package500mW TstgStorage Temperature 65 to + 150?C TLLead Temperature (8Second
5、 Soldering)260?C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic “P and D/DW” Packages: 7.0 mW/?C From 65?C To 125?C Ceramic “L” Packages: 12 mW/?C From 100?C To 125?C TRUTH TABLE Inputs Outputs Master ResetClockDisableLEOutputs 000No Cha
6、nge 000Advance 0X1XNo Change 010Advance 010No Change 00XXNo Change 0XXLatched 0XX1Latched 1XX0Q0 = Q1 = Q2 = Q3 = 0 X = Dont Care ? SEMICONDUCTOR TECHNICAL DATA Motorola, Inc. 1995 REV 3 1/94 ? BLOCK DIAGRAM This device contains protection circuitry to guard against damage due to high static voltage
7、s or electric fields. However, pre- cautions must be taken to avoid applications of any voltage higher than maximum rated volt- ages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ? (Vin or Vout) ? VDD. Unused inputs must always be tied to an
8、 appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. L SUFFIX CERAMIC CASE 620 ORDERING INFORMATION MC14XXXBCPPlastic MC14XXXBCLCeramic MC14XXXBDWSOIC TA = 55 to 125C for all packages. P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 751G 12 10 11 13 9 7 6 5 14
9、2 1 15 VDD = PIN 16 VSS = PIN 8 43 CLOCK LE DIS MR Q0 Q1 Q2 Q3 O.F. DS1 DS2 DS3 CIACIB 元器件交易网w w w . c e c b 2 b . c o m MOTOROLA CMOS LOGIC DATAMC14553B 2 ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) CharacteristicSymbol VDD Vdc 55?C25?C125?C UnitCharacteristicSymbol VDD VdcMinMaxMinTyp
10、#MaxMinMaxUnit Output Voltage“0” Level Vin = VDD or 0 VOL5.0 10 15 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 Vdc “1” Level Vin = 0 or VDD VOH5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Input Voltage“0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5
11、or 1.5 Vdc) VIL 5.0 10 15 1.5 3.0 4.0 2.25 4.50 6.75 1.5 3.0 4.0 1.5 3.0 4.0 Vdc “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) VIH 5.0 10 15 3.5 7.0 11 3.5 7.0 11 2.75 5.50 8.25 3.5 7.0 11 Vdc Output Drive Current (VOH = 4.6 Vdc)Source (VOH = 9.5 Vdc)Pin 3 (VOH = 13.5
12、Vdc) IOH 5.0 10 15 0.25 0.62 1.8 0.2 0.5 1.5 0.36 0.9 3.5 0.14 0.35 1.1 mAdc (VOH = 4.6 Vdc)Source (VOH = 9.5 Vdc) Other (VOH = 13.5 Vdc)Outputs 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.88 2.25 8.8 0.36 0.9 2.4 mAdc (VOL = 0.4 Vdc)Sink (VOL = 0.5 Vdc) Pin 3 (VOL = 1.5 Vdc) IOL5.0 10 15 0.5 1.1 1.8 0.4
13、0.9 1.5 0.88 2.25 8.8 0.28 0.65 1.20 mAdc (VOL = 0.4 Vdc)Sink Other (VOL = 0.5 Vdc)Outputs (VOL = 1.5 Vdc) 5.0 10 15 3.0 6.0 18 2.5 5.0 15 4.0 8.0 20 1.6 3.5 10 mAdc Input CurrentIin150.10.000010.11.0Adc Input Capacitance (Vin = 0) Cin5.07.5pF Quiescent Current (Per Package) MR = VDD IDD5.0 10 15 5.
14、0 10 20 0.010 0.020 0.030 5.0 10 20 150 300 600 Adc Total Supply Current* (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT5.0 10 15 IT = (0.35 A/kHz) f + IDD IT = (0.85 A/kHz) f + IDD IT = (1.50 A/kHz) f + IDD Adc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the ICs potential performance. *The formulas given are for the typical characteristics only at 25?C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: IT is in A (per pac
