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1、/* File: TYPEDEFS.H * TMS320x240 Test Bed Code * Texas Instruments, Inc. * Copyright (c) 1996 Texas Instruments Inc. * 11/05/96 Version 1.0 * Jeff Crankshaw */#ifndef TYPEDEFS_H#define TYPEDEFS_H#define FALSE 0#define TRUE 1typedef unsigned int WORD; /* 16bit data */typedef unsigned long DWORD; /* 3
2、2bit data */typedef volatile WORD * PORT;#define STR(x) #x#define OUTMAC(address,data) asm(” LDPK _”STR(data); asm(” OUT _”STR(data) ”,” STR(address)#define INMAC(address,data) asm(” LDPK _”STR(data); asm(” IN _”STR(data) ”,” STR(address)#define Int_Read(addr) * (int *) (addr)#define Int_Write(addr,
3、data) * (int *) (addr) = (data)#endif /* _TYPEDEFS */* File: C240.H * TMS320x240 Test Bed Code * Texas Instruments, Inc. * Copyright (c) 1996 Texas Instruments Inc. * 11/05/96 Version 1.0 * Jeff Crankshaw * * TMS320C240 Peripheral Register Addresses * */#ifndef c240_h#define c240_h#include ”typedefs
4、.h”/*/* definitions of I/O space macros */*/#define STR(x) #x#define OUTMAC(address,data) asm(” LDPK _”STR(data); asm(” OUT _”STR(data) ”,” STR(address)#define INMAC(address,data) asm(” LDPK _”STR(data); asm(” IN _”STR(data) ”,” STR(address)#define LED_LOC 000ch /* F240 EVM I/O space location for LE
5、Ds */*/* definitions of CPU core registers */*/#define IMR_REG ( PORT )0x0004 )#define IFR_REG ( PORT )0x0006 )/*/* External Memory Interface Registers */*/#define WSGR 0x0ffff/* Wait State Generator Register */*/* System Module Registers */*/#define SYSCR ( PORT )0x07018) /* System Module Control R
6、egister */#define SYSSR ( PORT )0x0701A) /* System Module Status Register */#define SYSIVR ( PORT )0x0701E) /* System Interrupt Vector Register */#define XINT1_CR ( PORT )0x07070) /* Int1 (type A) Control reg */#define NMI_CR ( PORT )0x07072) /* Non maskable Int (type A) Control reg */#define XINT2_
7、CR ( PORT )0x07078) /* Int2 (type C) Control reg */#define XINT3_CR ( PORT )0x0707A) /* Int3 (type C) Control reg */#define PDPINT_CR ( PORT )0x0742C) /* Power Drive Protection Int cntl reg */* System Interrupt Vector Register Address offsets */#define PHANTOM_INT_VECTOR 0x00#define NMI_INT_VECTOR 0
8、x02#define XINT1_INT_VECTOR 0x01#define XINT2_INT_VECTOR 0x11#define XINT3_INT_VECTOR 0x1f#define SPI_INT_VECTOR 0x05#define SCI_RX_INT_VECTOR 0x06#define SCI_TX_INT_VECTOR 0x07#define RTI_INT_VECTOR 0x10#define PDP_INT_VECTOR 0x20#define EV_CMP1_INT_VECTOR 0x21#define EV_CMP2_INT_VECTOR 0x22#define
9、 EV_CMP3_INT_VECTOR 0x23#define EV_SCMP1_INT_VECTOR 0x24#define EV_SCMP2_INT_VECTOR 0x25#define EV_SCMP3_INT_VECTOR 0x26#define EV_T1PER_INT_VECTOR 0x27#define EV_T1CMP_INT_VECTOR 0x28#define EV_T1UF_INT_VECTOR 0x29#define EV_T1OF_INT_VECTOR 0x2a#define EV_T2PER_INT_VECTOR 0x2b#define EV_T2CMP_INT_V
10、ECTOR 0x2c#define EV_T2UF_INT_VECTOR 0x2d#define EV_T2OF_INT_VECTOR 0x2e#define EV_T3PER_INT_VECTOR 0x2f#define EV_T3CMP_INT_VECTOR 0x30#define EV_T3UF_INT_VECTOR 0x31#define EV_T3OF_INT_VECTOR 0x32#define EV_CAP1_INT_VECTOR 0x33#define EV_CAP2_INT_VECTOR 0x34#define EV_CAP3_INT_VECTOR 0x35#define EV_CAP4_INT_VECTOR 0x36#define AC2_INT_VECTOR 0x04/*/* Digital I/O Registers */
