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1、William Stallings Computer Organization and Architecture7th EditionChapter 13Reduced Instruction Set Computers1Chapter 13Reduced Instruction Set ComputersKey terms CISC complex instruction set computerRISC reduced instruction set computerDelayed branchDelayed loadHLL high-level languageRegister file
2、Register window SPARC2Major Advances in Computers(1)The family conceptIBM System/360 1964DEC PDP-8Separates architecture from implementationMicroporgrammed control unitIdea by Wilkes 1951Produced by IBM S/360 1964Cache memoryIBM S/360 model 85 19693Major Advances in Computers(2)Solid State RAM(See m
3、emory notes)MicroprocessorsIntel 4004 1971PipeliningIntroduces parallelism into fetch execute cycleMultiple processors4The Next Step - RISCReduced Instruction Set ComputerKey featuresLarge number of general purpose registersor use of compiler technology to optimize register useLimited and simple ins
4、truction setEmphasis on optimising the instruction pipeline5Comparison of processors6Driving force for CISCSoftware costs far exceed hardware costsIncreasingly complex high level languagesSemantic gapLeads to:Large instruction setsMore addressing modesHardware implementations of HLL statementse.g. C
5、ASE (switch) on VAXSemantic: 语义的;语义学的 Gap 英音：gp 豁口,裂口 7Intention of CISCEase compiler writingImprove execution efficiencyComplex operations in microcodeSupport more complex HLLsease 减轻 HLL 缩写词缩写词 abbr. high-level language 【电脑】高级语言8Execution CharacteristicsOperations performedOperands usedExecution s
6、equencingStudies have been done based on programs written in HLLsDynamic studies are measured during the execution of the program9OperationsAssignmentsMovement of dataConditional statements (IF, LOOP)Sequence controlProcedure call-return is very time consumingSome HLL instruction lead to many machin
7、e code operationsAssignment 分配;指派,选派10Weighted Relative Dynamic Frequency of HLL Operations PATT82a Dynamic OccurrenceMachine-Instruction WeightedMemory-Reference WeightedPascalCPascalCPascalCASSIGN45%38%13%13%14%15%LOOP5%3%42%32%33%26%CALL15%12%31%33%44%45%IF29%43%11%21%7%13%GOTO3%OTHER6%1%3%1%2%1%
8、11OperandsMainly local scalar variablesOptimisation should concentrate on accessing local variablesPascalCAverageIntegerConstant16%23%20%ScalarVariable58%53%55%Array/Structure26%24%25%12Procedure CallsVery time consumingDepends on number of parameters passedDepends on level of nestingMost programs d
9、o not do a lot of calls followed by lots of returnsMost variables are local(c.f. locality of reference)13ImplicationsBest support is given by optimising most used and most time consuming featuresLarge number of registersOperand referencingCareful design of pipelinesBranch prediction etc.Simplified (
10、reduced) instruction set14Large Register FileSoftware solutionRequire compiler to allocate registersAllocate based on most used variables in a given timeRequires sophisticated program analysisHardware solutionHave more registersThus more variables will be in registers15Registers for Local VariablesS
11、tore local scalar variables in registersReduces memory accessEvery procedure (function) call changes localityParameters must be passedResults must be returnedVariables from calling programs must be restored16Register WindowsOnly few parametersLimited range of depth of callUse multiple small sets of
12、registersCalls switch to a different set of registersReturns switch back to a previously used set of registers17Register Windows cont.Three areas within a register setParameter registersLocal registersTemporary registersTemporary registers from one set overlap parameter registers from the nextThis a
13、llows parameter passing without moving datacont. 1.内容，所含之物 (contents) 2.继续的；不断的；连续的 18Overlapping Register Windows19Circular Buffer diagram主程序1子程序A2子程序B3子程序C4子程序D5子程序E6子程序F7子程序G20Operation of Circular BufferWhen a call is made, a current window pointer is moved to show the currently active register
14、windowIf all windows are in use, an interrupt is generated and the oldest window (the one furthest back in the call nesting) is saved to memoryA saved window pointer indicates where the next saved windows should restore to21Global VariablesAllocated by the compiler to memoryInefficient for frequentl
15、y accessed variablesHave a set of registers for global variables22Registers v CacheLarge Register FileCacheAlllocalscalarsRecently-usedlocalscalarsIndividualvariablesBlocksofmemoryCompiler-assignedglobalvariablesRecently-usedglobalvariablesSave/RestorebasedonprocedurenestingdepthSave/Restorebasedonc
16、achereplacementalgorithmRegisteraddressingMemoryaddressing23Referencing a Scalar - Window Based Register File24Referencing a Scalar - Cache25Referencing a Scalar - Window Based Register File26Compiler Based Register OptimizationAssume small number of registers (16-32)Optimizing use is up to compiler
17、HLL programs have no explicit references to registersusually - think about C - register intAssign symbolic or virtual register to each candidate variable Map (unlimited) symbolic registers to real registersSymbolic registers that do not overlap can share real registersIf you run out of real register
18、s some variables use memory27Graph ColoringGiven a graph of nodes and edgesAssign a color to each nodeAdjacent nodes have different colorsUse minimum number of colorsNodes are symbolic registersTwo registers that are live in the same program fragment are joined by an edgeTry to color the graph with
19、n colors, where n is the number of real registersNodes that can not be colored are placed in memory28Graph Coloring Approach29Graph Coloring Approach30Why CISC (1)?Compiler simplification? DisputedComplex machine instructions harder to exploitOptimization more difficult (开发)Smaller programs?Program
20、takes up less memory butMemory is now cheapMay not occupy less bits, just look shorter in symbolic formMore instructions require longer op-codesRegister references require fewer bits dispute 英音：dispju:t 争论;争执 simplification 1. 单纯化 2. 简单化 31Why CISC (2)?Faster programs?Bias towards use of simpler ins
21、tructionsMore complex control unitMicroprogram control store largerthus simple instructions take longer to executeIt is far from clear that CISC is the appropriate solution Bias 倾向,趋势 32RISC CharacteristicsOne instruction per cycleRegister to register operationsFew, simple addressing modesFew, simpl
22、e instruction formatsHardwired design (no microcode)Fixed instruction formatMore compile time/effort33RISC v CISCNot clear cutMany designs borrow from both philosophiese.g. PowerPC and Pentium IIphilosophies 哲学；观点34RISC PipeliningMost instructions are register to registerTwo phases of executionI: In
23、struction fetchE: ExecuteALU operation with register input and outputFor load and storeI: Instruction fetchE: ExecuteCalculate memory addressD: MemoryRegister to memory or memory to register operation35Figure 13.6cFigure 13.6c, three instructions can be overlapped, and the improvement is as much as
24、a factor of 3.I36Figure 13.6dE1: Register file readE2: ALU operation and register writeI37Effects of Pipelining38Optimization of PipeliningDelayed branchDelayed LoadLoop Unrolling39Optimization of Pipelining （1）Loop UnrollingReplicate body of loop a number of timesIterate loop fewer timesReduces loo
25、p overheadIncreases instruction parallelismImproved register, data cache or TLB locality unroll 展开，打开（卷着的东西） replicate 英音：replikeit 折叠;复制 iterate 英音：itreit 反复,重复 overhead 英音：uvhed日常开支，额外开销 40Optimization of Pipelining （2）Delayed branchDoes not take effect until after execution of following instructi
26、onThis following instruction is the delay slot41Normal and Delayed BranchAddressNormal BranchDelayed BranchOptimized Delayed Branch100LOADX,rALOADX,rALOADX,rA101ADD 1,rAADD 1,rAJUMP 105102JUMP 105JUMP 106ADD 1,rA103ADD rA,rBNOOPADD rA,rB104SUBrC,rBADD rA,rBSUBrC,rB105STORErA,ZSUBrC,rBSTORErA,Z106STO
27、RErA,Z42Use of Delayed BranchAddressNormal BranchDelayed BranchOptimized Delayed Branch100LOADX,rALOADX,rALOADX,rA101ADD1,rAADD1,rAJUMP105102JUMP105JUMP106ADD1,rA103ADDrA,rBNOOPADDrA,rB104SUBrC,rBADDrA,rBSUBrC,rB105STORErA,ZSUBrC,rBSTORErA,Z106STORErA,Z43Optimization of Pipelining （3）Delayed LoadReg
28、ister to be target is locked by processorContinue execution of instruction stream until register requiredIdle until load completeRe-arranging instructions can allow useful work whilst loading4480486 Instruction Pipeline Examples45Controversy (1)Quantitativecompare program sizes and execution speedsQ
29、ualitativeexamine issues of high level language support and use of VLSI real estate controversy 英音：kntrv:si 争论,辩论;争议 quantitative 定量的 qualitative 定性的 estate 英音：isteit 财产,资产 46Controversy (2)ProblemsNo pair of RISC and CISC that are directly comparableNo definitive set of test programsDifficult to se
30、parate hardware effects from complier effectsMost comparisons done on “toy” rather than production machinesMost commercial devices are a mixture47Required ReadingStallings chapter 13Manufacturer web sites48ControversyQuantitativecompare program sizes and execution speedsQualitativeexamine issues of
31、high level language support and use of VLSI real estateProblemsNo pair of RISC and CISC that are directly comparableNo definitive set of test programsDifficult to separate hardware effects from complier effectsMost comparisons done on “toy” rather than production machinesMost commercial devices are a mixture49Required ReadingStallings chapter 13Manufacturer web sites50
