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1、RTL设计概述1TipsDigitalsystemVerilogbasicstructureCodingstyle2DigitalsystemRTL在整个数字系统设计中的地位无论是CPU还是声卡芯片还是基带芯片RTL设计是整个数字系统设计的根基3ARM11corestructure4HelloworldC语言5Helloworld汇编语言6Helloworld机器码7zynq8功能要求功能要求行为设计（行为设计（RTL）Sing off是是行为仿真行为仿真综合、优化综合、优化网表网表时序仿真时序仿真布局布线布局布线版图版图后仿真后仿真否否是是否否否否是是IC design flow：9Veri
2、log basic structureKeywordsinitial,always,assign,ifelse,case,whileloop10RTLRTL or the Register Transfer Level is the most popular form of high level design specification. An RTL description of a design describes the design in terms of transformation and transfer of logic from one register to another
3、. Logic values are stored in registers where they are evaluated through some combinational logic, and then re-stored in the next register.11Basic Coding Practices General Naming Conventions :Use meaningful names for signals, ports, functions, and parameters. For example, do not use ra for a RAM addr
4、ess bus. Instead, use ram_addr.Use the name clk for the clock signal.For standardization, we recommend that you use _n to indicate an active low signalUse the name rst for reset signals. If the reset signal is active low, use rst_n 1213Headers in Source FilesAuthorDescription of function and list of
5、 key features of the moduleDate the createdModification history including date, name of modifier, and description of the change1415Use CommentsUse comments appropriately to explain all processes, functionsUse comments to explain ports, signals, and variables, or groups of signals or variables.Use co
6、mments to explain FSM16IndentationUse indentation of 2 spaces. Larger indentation (for example, 8 spaces) restricts line length when there are several levels of nesting.Avoid using tabs. Differences in editors and user setups make the positioning of tabs unpredictable and can corrupt the intended in
7、dentation. 17Port OrderingInputs: Clocks Resets Enables Other control signals Data and address linesOutputs: Clocks Resets Enables Other control signals Data18Port MapsAlways use explicit mapping for ports and generics, using named association rather than positional association. Leave a blank line b
8、etween the input and output ports to improve readability.19LoopsUse loops and arrays for improved readability of the source code. For example, describing a shift register, PN-sequence generator, or Johnson counter with a loop construct can greatly reduce the number of lines of source code while stil
9、l retaining excellent readability20Hard-Coded Numeric Values Do Not Use Hard-Coded Numeric Values21Use Technology-Independent LibrariesAvoid instantiating gates in the design. Gate-level designs are very hard to read, and thus difficult to maintain and reuse. If technology-specific gates are used, t
10、hen the design is not portable to other technologies.If you must use technology-specific gates, then isolate these gates in a separate module. This will make it easier to modify these gates as needed for different technologies.22Clocks and ResetsRTLPATH23Avoid Mixed Clock EdgesAvoid using both posit
11、ive-edge and negative-edge triggered flip-flops in your designIf you must use both positive-edge and negative-edge triggered flip-flops in your design, 1) be sure to model the worst case duty cycle of the clock accurately in synthesisand timing analysis.2)be sure to document the assumed duty cycle i
12、n the user documentation. 3)it may be useful to separate them into different modules. This makes it easier to identify the negative-edge flops, and thus to put them in different scan chains.24Avoid Gated ClocksAvoid gated clocks in your design. Clock gating circuits tend to be technology specific an
13、d timing dependent. Improper timing of a gated clock can generate a false clock or glitch, causing a flip-flop to clock in the wrong data. Also, the skew of different local clocks can cause hold time violations.If you must use a gated clock, or an internally generated clock or reset, keep the clock
14、and/or reset generation circuitry as a separate module“How To Successfully Use Gated Clocking in an ASIC Design”25Clk skew26Set-up time & Hold-time27Metastability28Avoid Internally Generated ClocksU2 cannot be clocked during scan-in, test, or scan-out, and cannot be made part of the scan chain becau
15、se it is clocked by an internally generated clock29Clock Generation30Avoid Internally Generated ResetsAvoid internally generated, conditional resets if possible. Generally, all the registers in the macro should be reset at the same time. This approach makes analysis and design much simpler and easie
16、r.31Infer registers with synchronous reset32Infer registers with asynchronous reset33Asynchronous reset34Asynchronous reset“Asynchronous & Synchronous Reset Design Techniques3536Avoid LatchesAvoid using any latches in your design.To check your design for latches, compile the design (with no constrai
17、nts for a quick compile) and use the report_cells command to check for latches.37Avoid LatchesAssign default values at the beginning Assign outputs for all input conditionUse else for the final priority branch38Avoid Combinational FeedbackAvoid combinational feedback; that is, the looping of combina
18、tional processes39Avoid Combinational Feedback40Tri-stateAvoid Tri-state in block design 41Specify Complete Sensitivity ListsInclude a complete sensitivity list in each of your process (VHDL) or always (Verilog) blocks.Mismatch of simulation and synthesis result“RTL Coding Styles That Yield Simulati
19、on and Synthesis Mismatches”Sensitivity List and Simulation PerformanceMake sure your process sensitivity lists contain only necessary signals,as defined in the sections above. Adding unnecessary signals to the sensitivity list slows down simulation.42Blocking and Nonblocking AssignmentsWhen writing
20、 synthesizable code, always use nonblocking assignments in always (posedge clk) blocks. Otherwise, the simulation behavior of the RTL and gate-level designs may differ.“Nonblocking Assignments in Verilog Synthesis, Coding Styles “43Blocking and Nonblocking Assignments4445Blocking and Nonblocking Ass
21、ignmentsAssign =Always(posedge clk) =always * =46Case Statements versus if-then-else Statements47if-then-else Statements48Case Statements“full_case parallel_case the Evil Twins of Verilog Synthesis”49Case Statements versus if-then-else StatementsThe multiplexer is a faster circuit. Therefore, if the
22、 priority-encoding structure is not required, we recommend using the case statement rather than an if-then-else statement. In a cycle-based simulator, the case statement also simulates faster than the if-then-else statement.50Coding State Machines“State Machine Coding Styles for Synthesis”51Register
23、 All OutputsFor each block of a hierarchical design, register all output signals from the block52Locate Related Combinational Logic in a Single ModuleKeep related combinational logic together in the same module.53Group combinational logic54Arithmetic Operators: Merging Resources55Eliminate Glue Logi
24、c at the Top Level56Asynchronous LogicAvoid asynchronous logic.If asynchronous logic is required in the design, partition the asynchronous logic in a separate module from the synchronous logic.“Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog” Tool: spyglass(cdc check
25、)57Synchronization using two DFFs58Synchronizer59Slow domain between fast domain60Data synchronizaitonDual port memory ,FIFO“Simulation and Synthesis Techniques for AsynchronousFIFO Design”61FIFO62FIFO63Partitioning for Synthesis Runtime“Synthesis Methodology for Large Designs - Design Compiler”Overconstraining a design is one of the biggest causes of excessive runtime.By grouping logic by design goals,64Designing with MemoriesFPGA: coregeneror DC: Memory CompilerResister Memory65Thanks66
