《3DTSVTEST调研报告》由会员分享，可在线阅读，更多相关《3DTSVTEST调研报告（33页珍藏版）》请在金锄头文库上搜索。
1、3D-TSV 测试调研报告测试调研报告马鹤2011/8/133D stacked ICsTo address the ever increasing need for low cost, high density devices a new industry design paradigm has emerged. 3D stacked IC (SIC) using Through Silicon Via (TSV) interconnects offers the opportunity to integrate multiple ICs at lower cost and silicon
2、footprint than conventional System in Package (SiP) technologies.Due to the new advanced manufacturing processes and physical access limitations of the TSVs, it is necessary for us to know the new characterizations of the TSVs.Test ContentElectrical Characterization of 3D TSV 、TSV DC characterizatio
3、n 、AC characterization 、High frequency characterizationEquivalent thermal conductivity of TSVTest for 3D chips 、DC CharacterizationA. TSV resistance For an accurate measurement of TSV resistance, 4-point Kelvin resistor configurations are adoptedDC Characterizationisolated TSVs show some voids or in
4、terfaces between the TSV and the landing pad, which are affecting the TSV contact resistance. This problem is absent in the dense TSV structures; causes are still under investigation.DC CharacterizationB. TSV yield TSV matrix structures where each TSV in the array is accessible for electrical measur
5、ement have been implemented.DC Characterization Measurement results for a 8x8 TSV matrix with a) 10um and b) 20um pitch. TSV yield decreases with TSV pitch and is lower at the edge of both matrices. TSVs in the center of the array show a good contact with the landing pad; some Cu extrusion due to bo
6、nding is visible. A possible cause maybe occurs in the procedure of thinning the wafer, when some particles generated in the procedure were left in the peripheral TSVs.DC CharacterizationC.Leakage current The same matrix concept is extended to measure the leakage current to Si substrate and the brea
7、kdown voltage of each TSV insulator in the array by providing a substrate contact in proximity of each TSV; in this case, the landing pad connection is not necessary.Maybe the parasitic effect with the neighbor TSVs.、AC characterizationThe ring oscillator (RO) is a fundamental circuit to evaluate th
8、e performance of IC technologies and is used here to evaluate the impact of TSVs on the RO delay and power.AC characterizationFor simulations, a simple lumped RC model is adopted for the TSV 4, calibrated with the measured values of TSV resistance and capacitanceHigh frequency characterizationA .Tes
9、t Structure （1）The de-embedding method to accurately account for the TSV RF test-structures. There are four steps in this method: a. The TSVs were characterized on a wide frequency range by S-parameters measurements; b. The second step is performed using measurements on specific test structures as O
10、pen, Short and Thru devices; c. Then, in third step an equivalent TSV electrical model can be directly extracted after a transformation of the TSV measured S scattering matrix as a ABCD transfer matrix. d. A last calculation step based on a -shaped equivalent model allowed to transform ABCD into TSV
11、 dual chain RLCG parameters. This electrical model of via should not be simply composed of serial inductance and resistance but also take into account silicon substrate effects with a capacitance and conductance.小结这种测试结构的建立过程较为复杂，需要考虑到各种的TSV结构（open，short，through）使得建模的过程需要很多的外界辅助设备。但结构中各种参数值比较精确，而且不仅
12、考虑到TSV自身的电阻和电感，同时还包含了TSV与衬底间的寄生效应。从上图可以看出测试的结果比较精确，各种测试参数基本与实际一致。High frequency characterization（2）Physical model of TSV The analytic equations are derived from the physical configuration with the design parameters. Therefore, each equation is a function of the variables from the design parameters.小
13、结这种近似测试结构的建立较为简单，建立的过程更易懂，结构中的各种参数只与TSV的物理参数有关，使得建模的过程比较独立。但是，实际工艺不会总是严格遵循所设计的尺寸，实际的参数与设计的参数不会严格一致，由此导致所建的测试结构参数不太准确，上图中表现出的实测与建模的测量结果之间存在约5%的误差。High frequency characterization（3）、Impact ModelTo measure the impedance of a single via, we designed a one-port, 50-, ground-signal- ground coplanar test s
14、tructure with the via under test at the end of the signal line。The ground pads are shorted by 30 substrate vias to the backside Cu ground plane in order to reduce the impedance of the ground pads.S-parameters of the substrate vias were measured from 50 MHz to 50 GHz and converted to . The series res
15、istance and inductance of the test structure pads were not de-embedded, so the actual impedance of a via is lower than that measured.The series resistance and inductance of the test structure pads were not de-embedded, so the actual impedance of a via is lower than that measured。The rise in the real
16、 part at frequencies greater than 5 GHz represents an increase in resistance due to the skin effect. The skin effect is also responsible for the decline in inductance.High frequency characterizationB、coupling effect It is widely-known that coupling exists between adjacent through-silicon vias (TSVs)
17、 in 3D ICs. Since this TSV-to-TSV coupling is not negligible, it is highly likely that TSV-to-TSV coupling affects crosstalk significantly.实际中，TSV不会一直独立存在，而是许多的TSV以一定的方式排列在silicon interposer中。此时，由于各个TSV相互接近会使TSV之间出现耦合现象。Coupling effects会对TSV的电阻、电感、寄生电容等参数产生影响。这一点在以上的两种建模方式中似乎都未被考虑到。High frequency ch
18、aracterizationC. Equivalent thermal conductivity of TSV芯片封装的测试工作中，除了要测试芯片的电路完整、正确外，关于芯片的散热能力也是需要特别注意的。It is well known that without the TSV, the thermal conductivity of the silicon interposer is isotropic. While with TSV, the thermal conductivity of the silicon interposers becomes anisotropic, i.e.,
19、 the thermal conductivity in planar directions (x, y) ( eq xy k , ) is not equal to that in normal direction (z) ( eq z k , ).Modeling for TSV interposerFirstly, create the geometry of TSV interposer with different TSV design parameters, then set the boundary conditions and simulate the temperature
20、distribution.After obtained the temperature distribution, the equivalent thermal conductivity can be calculated using equations (1) and (2).经研究发现Pitch 、aspect ratio、plating thickness、filler material of the TSV，have an affect on the equivalent thermal conductivity of the TSV.Modeling for the packageF
21、rom the results of simple analysis, it can be found that although the silicon interposer increases the thermal path of the package, while due to thermal spreading resistance, the total thermal resistance of the package with silicon interposer is less than that of the package without silicon interpos
22、er, and that indicates the TSV interposer improves the thermal performance of the package.Test for 3D chipsConventional single-die chips have two natural test moments:(1) wafer test (also referred to as e-sort) takes place after wafer fabrication and before assembly and packaging, and (2) packaged t
23、est takes place after assembly and packaging.3D-SICs have many more natural test moments. We distinguish between (1) pre-bond die tests, (2) post-bond stack tests, and (3) the packaged test.Test for 3D chipsThis test flow is such that after every manufacturing operation there is a subsequent test ex
24、ecuted, based on the idea that it is best to catch defects as early as possible, before they lead to further costs downstream.Test for 3D chips3D Wafer Test Challenges As discussed in the previous section, a 3D test flow contains potentially many more wafer tests for carrying out pre-bond die tests
25、and post-bond stack tests on intermediate product stages. Pre-bond die testing and post-bond stack testing both have their specific challenges with respect to wafer test access.(1) Pre-Bond Die Test Wafer Access For pre-bond die test wafer access, we distinguish between the bottom die and the other
26、(non-bottom) dies. If we want to perform pre-bond die tests on the non-bottom dies, new solutions need to be developed. The following solution approaches are being explored. Additional probe pads Probe technology improvement Contactless wafer probingTest for 3D chips(2). Post-Bond Stack TestWafer Ac
27、cessOn top of the bottom wafer, stacks consisting of one or multiple dies stick out. If that top side is the probe side of the wafer, the stacks might obstruct the contact view, making probe needle positioning difficult (see Figure (a). Also, during probe needle movement, we need to make sure that t
28、he needles do not collide with the stacks (see (b). On the other side, if we probe on the bottom side of the wafer, the stacks create a very non-planar surface, which is difficult to keep stable on the chuck. It is still a matter of on-going research to resolve these issues.Test for 3D chips3D On-Ch
29、ip DfT ArchitectureThe primary role of on-chip Design-for-Testability (DfT) is to provide controllability and observability from the chip I/Os into the heart of the chip design and vice versa.总结报告中介绍了关于TSV各方面特性的测试方法与测试结果。（1）、通过kelvin 结构和矩阵结构测试TSV的低频特性，如电阻、合格率和漏电流等；（2）、利用电路的延时和谐振搭建电路来测试基于silicon interposer的TSV的延迟特性；（3）、介绍了两种TSV的高频模型，并对这两种测试结构进行简单分析和比较；（4）、考虑到TSV之间耦合效应的影响，对耦合效应可能带来的影响进行了简单的分析；（5）、介绍了关于3D TSV package 的热效应的测量与分析；（6）、从整体上介绍了3D IC测试的基本流程与面临的一些问题，以及on-chip Design-for-Testability (DfT)电路的简介。
