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1、附录B 翻译原文Electronic design automationKeyword EDA; IC;VHDL language; FPGAPROCESS DESCRIPTION Three obstacles in particular bedevil ic designers in this dawn of the system on a chip. The first is actually a shortfall-the hardware and software components of the design lack a unifying language. Then, as
2、the number of logic gates per chip passes the million marks, verification of a designs correctness is fast becoming more arduous than doing the design itself. And finally, not only gate counts but chip frequencies also are climbing, so that getting a design to meet its timing requirements without to
3、o many design iterations is a receding goal. As is the wont of the electronic design automation (EDA) community, these concerns are being attacked by start-up companies led by a few individuals with big ideas and a little seed money.PARLEZ-VOUS SUPERLOG?A system on a chip comprises both circuitry an
4、d the software that runs on it. Such a device may contain an embedded processor core running a software modem. Most often, after the chips functionality is spelled out, usually on paper, the hardware com- potent is handed off to the circuit designers and the software is given to the pro- grammars, t
5、o meet up again at some later date. The part of the chips functionality that will end up as logic gates and transistors is writ- ten in a hardware design language-Virology or VHDL, while the part that will end up as software is most often described in the programming language C or C+. The use of the
6、se disparate languages hampers the ability to describe, model, and debug the circuitry of the IC and the software in a coherent fashion.It is time, many in the industry believe, for a new design language that can cope with both hardware and software from the initial design specification right throug
7、h to final verification. Just such a new language has been developed by Co-Design Automation Inc., San Jose, Calif. Before launching such an ambitious enterprise, cofounders Simon Davidmann, who is also chief operating officer, and Peter Flake ruled out the usefulness of extending an existing langua
8、ge to meet system-on-chip needs. Among the candidates for extension were C, C+, Java, and Verilog. A design language should satisfy three requirements, maintained Davidmann. It should unify the design process. It should make designing more efficient. And it should evolve out of an existing methodolo
9、gy. None of the existing approaches filled the bill. So Davidmann and Flake set about developing new co-design language called Superlog. A natural starting point was a blend of Virology and C since from an algorithm point of view, a lot of Virology is built on C, explained Davidmann. Then they spice
10、d the blend with bits and pieces of VHDL and Java. From Virology and VHDL, Superlog has acquired the ability to describe hardware aspects of the design, such as sequential, combinatorial, and multivalued logic. From C and Java it inherits dynamic processes and other software constructs. Even functio
11、ns like interfaces, protocols, and state machines, which till now have often been done on paper, can be described in the new language. To support legacy code written in a hardware description or programming language, Superlog allows both Virology and C modules to be imported and used directly.It is
12、important for the language to be in the public domain, according to Davidmann. The company has already begun to work with various standards organizations to this end. Not to be overlooked is the need for a suite of design tools based on the language. Recently Co-Design identified a number of electro
13、nic design automation companies, among them Magma Design Automation, Sente, and Viewlogic, that will develop tools based on Superlog. Co-Design will also develop products for the front end of the design process.ARACE TO THE FINISH Not everyone is convinced that a new language is needed. SystemC, a m
14、odeling platform that extends the capabilities and advantages of C/C+ into the hardware domain has been proposed as an alternative. Such large and powerful companies as Synopsys, Coware, Lucent Technologies, and Texas Instruments have banded together under the Open SystemC Initiative to promote thei
15、r version of the next-generation design platform. To get SystemC off to a running start, the group offers a modeling platform for download off their Web site free of charge. Their hope is also to make their platform the de facto standard. The rationale for developing SystemC was straightforward, acc
16、ording to Joachim Kunkel, general manager and vice president of the System Level Design Business Unit at Synopsys. It was to have a standard language in which semiconductor vendors, IP vendors, and system houses could exchange system-level IP and executable specifications, and the electronic design automation industry could develop interoperable tools. Supporters of SystemC believe that the would-be standard has to be based on C+ because it allo
