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1、机械与电气工程学院 毕业设计（论文）外文翻译所在学院： 机电学院 班 级： 姓 名： 学 号： 指导教师： 合作导师： 2013 年 10 月 31 日Voltage Controlled Ring Oscillator Design with Novel 3 Transistors XNOR/XOR GatesManoj Kumar1, Sandeep Kumar Arya1, Sujata Pandey21Department of Electronics & Communication Engineering Guru Jambheshwar, University of Science
2、 & Technology, Hisar, India2Department of Electronics & Communication Engineering, Amity University, Noida, IndiaE-mail: manojtalejagjust.orgReceived April 14, 2011; revised May 6, 2011; accepted May 13, 2011AbstractIn present work, improved designs for voltage controlled ring oscillators (VCO) usin
3、g three transistors XNOR/XOR gates have been presented. Supply voltage has been varied from 1.8 - 1.2 V in proposed de-signs. In first method, the VCO design using three XNOR delay cells shows frequency variation of 1.900 - 0.964 GHz with 279.429 - 16.515 W power consumption variation. VCO designed
4、with five XNOR de-lay cells shows frequency variation of 1.152 - 0.575 GHz with varying power consumption of 465.715 - 27.526 W. In the second method VCO having three XOR stages shows frequency variation 1.9176 - 1.029 GHz with power consumption variation from 296.393 - 19.051 W. A five stage XOR ba
5、sed VCO design shows frequency variation 1.049 - 0.565 GHz with power consumption variation from 493.989 - 31.753 W. Simulations have been performed by using SPICE based on TSMC 0.18m CMOS technology. Power con-sumption and output frequency range of proposed VCOs have been compared with earlier repo
6、rted circuits and proposed circuits shows improved performance.Keywords: CMOS, Delay Cell, Low Power, VCO, XOR and XNOR Gates1. IntroductionThe Phase locked loops (PLL) are widely used circuit component in data transmission systems and have exten-sive applications in data modulation, demodulation an
7、d mobile communication. Voltage control oscillators (VCO) are the critical and necessary building blocks of these PLL systems. Two widely used VCOs types are LC tank based and CMOS ring circuits. Combination of inductor and capacitor consumes large layout area in LC tank based oscillators 1-3. CMOS
8、ring based oscillators have advantages due to ease of controlling the output frequency and no requirement for on chip inductors 4,5. CMOS based ring oscillators are easier to integrate and also gives wide tuning range. Due to flexibility of on chip integration, CMOS based ring oscillators have be-co
9、me essential building blocks in various battery oper-ated mobile communication systems. Rising requirement of portable devices like cellular phones, notebooks, per-sonal communication devices have aggressively en-hanced attention for power saving in these devices. Pow-er consumption in very large sc
10、ale integration (VLSI) systems includes dynamic, static power and leakage power consumption. Dynamic power consumption re-sults from switching of load capacitance between two different voltages and dependent on frequency of opera-tion. Static power is contributed by direct path short cir-cuits curre
11、nts between supply (Vdd) and ground (Vss) and it is dependent on leakage currents components 6,7. VCOs being the major components in PLL system and is responsible for most of the power consumption. Some draw back of ring based oscillators includes large power consumption, phase noise and the limit o
12、f highest achievable frequency. In modern VCOs design power consumption and output frequency range are significant performance metrics 8-13. A ring oscillator consist of delay stages, with output of last stage fed back to input of first stage. A VCO block diagram with single ended N-delay stages is
13、shown in Figure 1.The ring must provide a phase shift of 2 and unity voltage gain for oscillation occurrence. Each delay cell also gives a phase shift of /N, where N is number of delay stages. The remaining phase shift is provided by dc inversion using the inverter delay cells. For singleended oscil
14、lator design the odd numbers of delay stage are required for dc inversion. Frequency of oscillation with N-single ended delay stages is given by of fo =1/(2Ntd),where N is the number of delay stages and td is delay of each stage 9,14. Delay stages are the basic building blocks in any VCO design and
15、improved design of these delay cells will improve the overall perform-ances of VCO. Various types of delay cells have been reported for VCO design including multiple-feed- back loops, dual-delay paths and single ended delays. These delay cells have been implemented by various ap-proaches like simple inverter stage, latches, cross cou-pled cells etc. 15-18.In present work modified VCOs circuits with three transistor XNOR/XOR delay cells have been presented with reduced the power consumption and wide output frequency range. The pa
