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1、大规模数字逻辑题目： 流水灯控制 专 业 电子信息科学与技术 班 级 学 号 学生姓名 设计时间 教师评分 2013年 12 月 10 日目 录一、概述1二、设计目的1三、设计内容1四、设计原理图1五、引脚分配情况2六、源程序代码2VerilogHDL 程序：2分频器部分：5七、心得体会6八、参考文献6解决党委自身和基层党支部存在的的突出问题，发挥各村、社区、机关单位党支部在当前城市征迁、园区建设、招商引资、服务群众、维护稳定的作用，我镇党委高度重视，制定了切合临淮实际的活动实施方案，按照中央规定的活动步骤和要求扎实有效的开展了基层组织建设年活动。一、概述流水灯是一串按一定的规律像流水一样连续
2、闪亮，流水灯控制是可编程控制器的一个应用，其控制思想在工业控制技术领域也同样适用。流水灯控制可用多种方法实现，但对现代可编程控制器而言，基于EDA技术的流水灯设计也是很普遍的。二、设计目的1、熟悉利用Quartus II 开发数字电路的基本流程和Quartus II 软件的相关操作。2、掌握基本的设计思路，软件环境参数配置，仿真，管脚分配，利用JTAG/AS进行下载等基本操作。3、了解VerilogHDL 语言设计或原理图设计方法。4、通过本此设计，了解流水灯的工作原理，掌握其逻辑功能及设计方法。三、设计内容1、用VerilogHDL语言设计一个流水灯，输入0的时候ledled7，1Hz正向流
3、水3次，然后全亮；然后2Hz逆向流水5次全亮；循环。输入1的时候led0led7,0.5Hz奇数流水2次，全亮，1Hz偶数流水4次，全亮，然后循环。2、用QuartusII 软件进行编译，仿真，下载到实验平台进行验证。四、设计原理图 en为可调输入，输出为8位数据，为流水灯实验，试用8个LED指示灯来表示，具体引脚分配见下。五、引脚分配情况六、源程序代码VerilogHDL 程序：module LED( clk,led,en ); input clk; input en; output 7:0led;/ 输出端口定义为寄存器型 reg 7:0 led; reg 8:0 state1; reg
4、8:0 state2; always (posedge clk )/ always语句，表示每当CLK的上升沿到来时，完成begin-end之间语句的操作 if(!en) begin state2 = 0; state1 = state1 + 1; / one clk,one state case(state1) 1,2: led = 8b; /1-7 zhengxu,3bian 3,4: led = 8b; 5,6: led = 8b; 7,8: led = 8b; 9,10: led = 8b; 11,12: led = 8b; 13,14: led = 8b; 15,16: led =
5、8b; 17,18: led = 8b; 19,20: led = 8b; 21,22: led = 8b; 23,24: led = 8b; 25,26: led = 8b; 27,28: led = 8b; 29,30: led = 8b; 31,32: led = 8b; 33,34: led = 8b; 35,36: led = 8b; 37,38: led = 8b; 39,40: led = 8b; 41,42: led = 8b; 43,44: led = 8b; 45,46: led = 8b; 47,48: led = 8b; 49: led = 8b; /quanliang
6、 50: led = 8b; 51: led = 8b; 52: led = 8b; 53: led = 8b; 54: led = 8b; 55: led = 8b; 56: led = 8b; 57: led = 8b; 58: led = 8b; 59: led = 8b; 60: led = 8b; 61: led = 8b; 62: led = 8b; 63: led = 8b; 64: led = 8b; 65: led = 8b; 66: led = 8b; 67: led = 8b; 68: led = 8b; 69: led = 8b; 70: led = 8b; 71: l
7、ed = 8b; 72: led = 8b; 73: led = 8b; 74: led = 8b; 75: led = 8b; 76: led = 8b; 77: led = 8b; 78: led = 8b; 79: led = 8b; 80: led = 8b; 81: led = 8b; 82: led = 8b; 83: led = 8b; 84: led = 8b; 85: led = 8b; 86: led = 8b; 87: led = 8b; 88: led = 8b; 89: led = 8b; 90: led = 8b; 91: begin led = 8b;state1=0;end default: state1 = 0; endcase end else begin state1 = 0; state2 = state2 + 1; / one clk,one state case(state2) 1,2,3,4: led = 8b; 5,6,7,8: led = 8b; 9,10,11,12: led = 8b; 13,14,15,16: led = 8b; 17,18,19,20: led = 8b; 21,22,23,24: led = 8b; 25,26,27,
