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1、Design of CMOS analog Integrated Circuits,Layout,2019/6/26,2,Outline,1. General Layout Considerations 2. Analog Layout Techniques 3. Substrate Coupling,2019/6/26,3,1 1. General Layout Considerations,Layout,设计规则：最小宽度、间距、包围、延伸,latchup、ESD、天线效应,2019/6/26,4,2 . Analog Layout Techniques,2.1 Multifinger T
2、ransistors,叉指晶体管可以降低S/D结面积和栅电阻； 设计时，栅电阻应小于其跨导的倒数；低噪中，栅电阻是1/gm的1/5到1/10,叉指数N周边电容CP,2019/6/26,5,2.2 Symmetry,2019/6/26,6,2.2 Symmetry,2019/6/26,7,2.2 Symmetry,2019/6/26,8,2.3 Reference Distribution,2019/6/26,9,2.3 Reference Distribution,Reduce mismatch,2019/6/26,10,2.4 Passive Devices,Resistors,2019/6
3、/26,11,2.4 Passive Devices,Resistors,NWELL电阻,2019/6/26,12,2.4 Passive Devices,Resistors,工艺导致的变化20% 30%,2019/6/26,13,2.4 Passive Devices,Capacitors,工艺导致的变化5% 20%,2019/6/26,14,2.4 Passive Devices,Inductors,片上螺旋电感: D: 直径 W: 线宽 S: 间距 N: 圈数 参数: D, 决定于面积约束. W, S 和 N根据优化以下参数得到 Desired inductance L High qua
4、lity factor Q High self-resonant frequency fSR,2019/6/26,15,2.4 Passive Devices,Inductors,D: 直径: D Q but fsr as parasitic capacitance between substrate and the spiral increases. A good design usually has D Wopt, skin effects appear in metal traces, increasing Rs. A good design uses 10 mm W 20 mm S:
5、间距 Spacing should be as small as possible. S L as mutual inductance decreases. Use minimum metal spacing in the technology N: 圈数 Use a value that gives a layout convenient to work other parts of circuits,2019/6/26,16,2.5 Interconnects,Differential operation: converts most of crosstalk to common-mode
6、 disturbance.,“shieldling”,IR drop,2019/6/26,17,2019/6/26,18,3. Substrate Coupling,Substrate coupling effect,2019/6/26,19,Methods of minimizing the effect of substrate noise,Differential mode,Digital signals and clocks should be distributed in complementary form.,Cirital operations, e.g. sampling a
7、signal,The inductance of the bond wire connected to the substrate should be minimized.,Guarding ring,2019/6/26,20,Methods of minimizing the effect of substrate noise,Ground bounce (地反射),由于电路的瞬间大电流，造成相对于“外部地”的衬底电压反射,因此，衬底与芯片内部的“地”连接到一起连接到外部，并且模拟与数字分开,2019/6/26,21,Methods of minimizing the effect of s
8、ubstrate noise,Ground bounce,Which “ground” should the substrate be connect to?,与瞬态电流以及LA、LD的大小决定。,2019/6/26,22,Methods of minimizing the effect of substrate noise,Ground bounce,由于地反射，单端输入的参考电位会受到严重影响。可采用差动的工作方式。,2019/6/26,23,Summary,Layout Techniques Design rules:设计者与foundry的interface Symmetry Substrate Coupling Minimizing the effect of substrate noise Ground bounce,
