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1、,AT91RM9200 Embedded Peripherals,External Bus Interface,Integrates three external memory controllers Static Memory Controller, SDRAM Controller and Burst Flash Controller Additional logic for SmartMedia and CompactFlash support Optimized external bus 16 or 32-bit data bus Up to 26-bit address bus, u
2、p to 64M Bytes addressable Up to 8 chip selects Optimized pin multiplexing to reduce latencies on external memories,External Bus Interface,Block Diagram,External Bus Interface,Static Memory Controller External memory mapping, 512M Bytes address space Up to 8 chip select lines 8 or 16-bit data bus By
3、te write or Byte select lines Remap of Boot Memory Programmable wait state generation, Data float time, Setup time Read/Write, Hold time Read/Write Compliant with LCD Module External Wait Request,External Bus Interface,SDRAM Memory Controller External memory mapping, 256M Bytes address space Support
4、s an SDRAM with two or four internal banks Supports an SDRAM with 16 or 32-bit data path Automatic refresh operation, refresh rate is programmable Supports self-refresh and low-power modes Read or Write burst length of one location Word, Half-word, Byte access Multibank Ping-pong access SDRAM power-
5、up initialization by software Refresh error interrupt,External Bus Interface,Burst Flash Controller 16-bit data bus Asynchronous or Burst mode read Byte, Half-word or Word accesses Asynchronous mode Half-word write accesses Programmable data access time Programmable latency after output enable Progr
6、ammable Burst Flash clock rate Two Burst Read Protocols: Clock Control Address Advance or Signal Controlled Multiplexed or Separate address and data buses,External Bus Interface,Compact Flash I/O mode : used for I/O peripherals like modems Attribute memory mode : (0 - 1FF) contains the card ID, manu
7、facturer ID Common memory mode : allows to store data in memory True IDE mode is not supported,Power Management Controller,PMC embeds and controls One main oscillator providing a frequency range 3 : 20 MHz One slow clock oscillator (32768 Hz) Two phase locked loops and dividers Clock prescalers PMC
8、provides clocks to the whole system Processor clock PCK : typically MCK but switched off when entering idle mode. Master clock MCK, it is available to the modules running permanently USB clocks UHPCK and UDPCK at 48MHz,Power Management Controller,Four operating modes Normal : processor and periphera
9、l clocks are enabled Idle : processor clock is disabled, waiting for interrupt, Peripheral clocks are enabled Slow : processor and peripherals run at slow clock Standby : combination of slow clock mode and idle mode.,Power Management Controller,Block Diagram,Advanced Interrupt Controller,AIC control
10、s the interrupt lines of an ARM processor Thirty-two individually maskable and vectored interrupt sources Source 0 is reserved for the fast interrupt input Source 1 is reserved for system peripherals (ST, RTC, PMC, DBGU ) Sources 2 to 31 control up to thirty embedded peripheral interrupts or externa
11、l interrupts. Programmable Edge-triggered or Level-sensitive internal sources Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive external sources AIC enables/disables independently the thirty-two sources,Advanced Interrupt Controller,Eight-level priority controller Handles pri
12、ority of the interrupt sources 1 to 31, the fast interrupt logic of the AIC has no priority controller Higher priority interrupts can be served during service of lower priority interrupt,Advanced Interrupt Controller,Vectoring One 32-bit vector register per interrupt source, fast interrupt included
13、Interrupt vector register reads the corresponding current interrupt vector (handler address) Branch in one single instruction to the right handler,Advanced Interrupt Controller,Fast forcing Redirects any normal interrupt source on the fast interrupt of the processor Unlike IRQs and FIQs, fast forced
14、 interrupts arent cleared automatically General interrupt mask Prevents interrupts from reaching the processor Processor can still be waken up even if the mask is set up Provides processor synchronization on events without having to handle an interrupt,Advanced Interrupt Controller,Interrupt nesting
15、 Handles a high priority interrupt during the service of a lower priority interrupt Current priority interrupt is pushed in an 8-level wide, embedded hardware stack Protect mode Allows to read the interrupt vector register without performing the associated automatic operations : stacking and clearin
16、g This is necessary when working with debug Interrupt stacking is performed by writing to the interrupt vector register,Advanced Interrupt Controller,Spurious interrupt Spurious vector is returned when the assertion of an interrupt does no longer exists when the IVR is read Application Block Diagram,Peripheral Data Controller,PDC transfers data between on-chip serial peripherals and on- and off-chip memories. On-chip serial peripherals UART, USART, SSC, SPI, MCI Using PDC avoids processor
