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1、触发器,寄存器, 记数器和简单处理器,延 边 大 学 工 学 院电 子 信 息 通 信 学 科许 一 男,报警系统的控制结构,2,时序电路: 由于输入信号发生变化, 从而使电路的状态随时间的进展发生一系列变化。,传感器,记忆电路,警 报,reset,on/off,简 单 的记 忆 电 路,3,A (0),B (1),if A = 0; B = 1,(0),锁 存 器Latch,4,基本锁存器 (Basic Latch),5,reset,set,Q,或非门组成的记忆电路(NOR),或非门组成的锁存器(latch),6,Q,R (reset),S (set),Qbar,电路图,特征表,(no Ch
2、ange),或非门组成的锁存器(Verilog HDL),7,module NOR_LATCH (R,S,Q,Qbar);input R, S;output Q, Qbar;nor U1 (Q, R, Qbar);nor U2( Qbar, S, Q); endmodule,或非门组成的锁存器(latch),8,R,S,1,0,1,0,1,0,1,0,Qa,Qb,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,时序仿真(1),9,module NOR_LATCH (R,S,Q,Qbar);input R, S;output Q, Qbar;nor U1 (Q, R, Qbar);
3、nor U2( Qbar, S, Q); endmodule,R,S=2b00,震荡现象,时序仿真(2),10,R,S=2b01,没有震荡现象,门控SR锁存器(clock控制输入信号),11,Q,R,S,Qbar,电路图,clock,R,S,no change,门控SR锁存器(Gated SR Latch),12,时序图(Timing Diagram),no change,Clk,1,0,R,1,0,S,1,0,Q,1,0,Q,1,0,特征表,门控SR锁存器(时序仿真),13,module test (clk,R,S,Q,Qbar);input clk, R, S;output Q, Qbar
4、;reg Rp, Sp;and U0 (Rp, clk, R);and U1 (Sp, clk, S);nor U2 (Q, Rp, Qbar);nor U3( Qbar, Sp, Q); endmodule,S=R=1, clk从1变成0 = 震荡现象 (尽量避免R=S=1),门控SR锁存器(Gated SR Latch),14,电路图,S,clk,R,Q,Q,图形符号,门控SR锁存器(Gated SR Latch),15,电路图,S,clk,R,Q,Q,图形符号,门控SR锁存器(Gated SR Latch),16,Qa,R,S,Qb,与非门实现电路图,clock,R,S,门控D锁存器(G
5、ated D Latch),17,Q,D(data),Q,电路图,clock,S,R,门控D锁存器(Gated D Latch),18,电路图,特征表,门控D锁存器的Verilog HDL编程,19,电路图,特征表,module D_latch (D, Clk, Q);input D, Clk;output reg Q; always (D, Clk)Q ,Q,Q,通用的储存单元,Qs,主从D触发器(Master-Slave D Flip-Flop),24,图形符号,D,Q,Q,clk,D,Qm,Q=Qs,25,电路图,D,clk,Q,Q,D,clk,Q,Q,D,clk,Q,Q,Qm,mast
6、er,slave,Qs,D触发器的Verilog HDL编程,module flipflop (D, Clk, Qm, Qs);input D, Clk;output reg Qm, Qs; always (posedge Clk) beginQm = D;Qs = Qm;end endmodule,D触发器的Verilog HDL编程,26,module flipflop (D, Clk, Q);input D, Clk;output reg Q; always (posedge Clk)Q ,Q,Q,沿触发的D触发器(Edge-Triggerd D Flip-Flop),27,图形符号,D
7、,Q,Q,有清零端和预置信号的D触发器(D Flip-Flop with Clear and Preset),28,图形符号,D,Q,Q,Q,Q,Clear,Preset,Clear,Clear,Preset,Clear,沿触发的D触发器(Edge-Triggerd D Flip-Flop),29,图形符号,Q,Q,D,clock,Preset,Clear,D,Q,Q,Clear,Preset,Clear,D,Q,Q,Clear,D,clk,D触发器的Verilog HDL编程,30,D,Q,Q,Reset,module flipflop (D, Clk, Reset, Q);input D,
8、 Clk, Reset;output reg Q; always (negedge Reset, posedge Clk)beginif (!Reset)Q =0;elseQ ,Q,Q,clk,Q,Q,T,特征表,T触发器(T Flip-Flop),32,图形符号,D,Q,Q,clk,Q,Q,D,Q,Q,T,T触发器(T Flip-Flop),33,D,Q,Q,clk,Q,Q,T,特征表,clk,T,Q,JK触发器(JK Flip-Flop),34,D,Q,Q,clk,Q,Q,K,特征表,J,D = JQ + KQ,JK触发器(JK Flip-Flop),35,D,Q,Q,clk,Q,Q,K,
9、特征表,J,图形符号,J,Q,Q,K,JK触发器的Verilog HDL,module JKff (CLK,J,K,Q);input CLK, J, K;output Q;reg Q;always (posedge CLK)case (J,K)2b01: Q Q=02b10: Q Q=12b11: Q Q=Qendcase endmodule,JK触发器的Verilog HDL (reset, set 功能),module JKff (CLK,J,K,Reset,Set,Q);input CLK, J, K, Reset, Set;output Q;reg Q;always (posedge
10、CLK or posedge Reset or posedge Set)if (Reset) Q Q=02b10: Q Q=12b11: Q Q=Qendcase endmodule,寄 存 器Register,38,移位寄存器(Shift Register),39,D,Q,Q,D,Q,Q,D,Q,Q,D,Q,Q,OUT,Q4,Q3,Q2,Q1,Input,Clk,4位移位Verilog HDL 编程,40,module muxdff(D0, D1, Sel, Clk, Q);input D0, D1, Sel, Clk;output reg Q;always (posedge Clk)if
11、(!Sel)Q = D0;elseQ = D1;endmodule,module shift4(R, L, w, Clk, Q);input 3:0 R;input L, w, Clk;output wire 3:0 Q;muxdff stage3 (w, R3, L, Clk, Q3);muxdff stage2 (Q3, R2, L, Clk, Q2);muxdff stage1 (Q2, R1, L, Clk, Q2);muxdff stage0 (Q1, R0, L, Clk, Q1);endmodule,41,module shift4(R, L, w, Clk, Q);input
12、3:0 R;input L, w, Clk;output wire 3:0 Q;muxdff stage3 (w, R3, L, Clk, Q3);muxdff stage2 (Q3, R2, L, Clk, Q2);muxdff stage1 (Q2, R1, L, Clk, Q2);muxdff stage0 (Q1, R0, L, Clk, Q1);endmodule,module shift4(R, L, w, Clk, Q);input 3:0 R;input L, w, Clk;output wire 3:0 Q;always (posedge Clk)if (L) Q = R;else beginQ0 = Q1;Q1 = Q2;Q2 = Q3;Q3 = w;endendmodule,4位移位Verilog HDL 编程,42,module shiftn(R, L, w, Clk, Q);parameter n=32;input n-1:0 R;input L, w, Clk;output wire n-1:0 Q;always (posedge Clk)if (L) Q = R;else beginfor (k = 0; k n-1; k = k + 1)Qk = Qk+1;Qn-1 = w;endendmodule,