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1、Copyright 1997 Altera CorporationVHDL Design Techniques for FLEX DevicesCopyright 1997 Altera CorporationAgendan Using IF - THEN Statements Efficiently n State Machine Coding Styles n Using Arithmetic Operators with MAX+PLUS II VHDL n The Importance of InstantiationCopyright 1997 Altera CorporationA
2、gendanUsing IF - THEN Statements Efficiently n State Machine Coding Styles n Using Arithmetic Operators with MAX+PLUS II VHDL n The Importance of InstantiationCopyright 1997 Altera CorporationUsing IF - THEN Efficientlyn Frequently Used VHDL Construct Provides Conditional Testing n Can Only Be Used
3、Inside a PROCESS Statement (Sequential Processing) n Sequential Processing Translates to Priority Encoding when Synthesized into LogicCopyright 1997 Altera CorporationIF - THEN Example 1PROCESS(a,B,R,S,T) BEGINIF a = 1 THEN Q IF Beer = 1 THEN Fae IF Beer = 1 THEN Fae IF Beer = 1 THEN Fae IF Beer = 1
4、 THEN Fae IF Beer = 1 THEN Fae IF Beer = 1 THEN Fae IF (Beer = 1 OR Tequila = 1) THEN Fae Fae IF Tequila = 1 THEN Fae Fae state state state state state state State state state state state state state next_state := s2;IF data = 0 THEN next_state := s1;END IF;WHEN s1 = next_state := s3;IF data = 0 THE
5、N next_state := s2;END IF;WHEN s2 = next_state := s3;IF data = 0 THEN next_state := s2;END IF;WHEN s3 = next_state := s4;WHEN s4 = next_state := s5;IF data = 0 AND sm_input = 0 THENnext_state := s6; END IF;WHEN s5 = next_state := s0;IF data = 0 AND sm_input = 1 THENnext_state := s5;ELSIF data = 0 AN
6、D sm_input = 0 THENnext_state := s6; END IF;WHEN s6 = next_state := s0;IF data = 0 AND sm_input = 1 THENnext_state := s5;ELSIF data = 0 AND sm_input = 0 THENnext_state := s6; END IF;END CASE;END IF;END PROCESS; END state_machine;Copyright 1997 Altera CorporationMoore State MachineState Machine Codin
7、g Styles: Summaryn Performance Advantages of Moore State Machines vs. Mealy State Machines Narrower Post-Register Output Decode Logic Dependent on State Bits Only (Inputs Not Required) Reduced Routing Resources Inputs Have Single Destination (Next State Decode Logic) State MachineState MachineOutput
8、 LogicInputsInputsOutputsOutputsExtra Routing ResourcesWider Decode LogicMealy State MachineMooreOutput LogicCopyright 1997 Altera CorporationState Machine Coding Styles: Summaryn RNS State Machine Benifits vs. Mealy C,D: IN Std_Logic_Vector(15 DOWNTO 0);Input : IN Std_Logic;Sum : OUT Std_Logic_Vect
9、or(15 DOWNTO 0); END Add_Ex1; ARCHITECTURE Behavior OF Add_Ex1 IS SIGNAL a_in1:Std_Logic_Vector(Num-1 DOWNTO 0); SIGNAL a_in2 : Std_Logic_Vector(Num-1 DOWNTO 0); BEGINPROCESS(a,B,C,D,Input)BEGINIF Input = 0 THENA_in1 0);ELSIF ClkEVENT AND Clk = 1 THENIF Dir = 1 THENTmp_Q 0);ELSIF ClkEVENT AND Clk =
10、1 THENIF Dir = 1 THENTmp_Q 0);ELSIF ClkEVENT AND Clk = 1 THENIF Dir = 1 THENTmp_Q 0);ELSIF ClkEVENT AND Clk = 1 THENIF Dir = 1 THENTmp_Q = Tmp_Q + 1;ELSETmp_Q = Tmp_Q - 1;END IF;END IF;END PROCESS; Q = Tmp_Q; END Behavior;n MAX+PLUS II 1 Adder, 1 Subtractor (16 Bit) 16 Registers 47 LEs+Registers+1-1
11、qrstclk+Copyright 1997 Altera CorporationLab 2: 16-Bit Up/Down Countern Open LAB2.VHD Similar to Example 2 Process Statement Uses Integers for Ease of Modification n Modify LAB2.VHD to Use 1 Adder/Subtractor You Will See a Significant Reduction in LE Usage Correct Implementation Will Infer an LPM up
12、/Down Counter Use GLOBAL SYNTHESIS STYLE = FAST when CompilingHint: Define the Data Flow Explicitly. Use “+” Only Once.Copyright 1997 Altera CorporationExample 2: 16-Bit Up/Down CounterENTITY Udcnt_2 ISPORT(Clk,Rst,Updn : IN Std_Logic;Q : OUT Std_Logic_Vector(15 DOWNTO 0); END Udcnt_2; ARCHITECTURE
13、Behavior OF Udcnt_2 IS SIGNAL Tmp_Q : Integer RANGE 0 TO 65535; SIGNAL Dir : Integer RANGE -1 TO 1; BEGINPROCESS(Clk,Rst)BEGINIF Rst = 0 THENTmp_Q = 0;ELSIF ClkEVENT AND Clk = 1 THENIF Updn = 1 THEN Dir = 1;ELSE Dir = (-1);END IF;Tmp_Q = Tmp_Q + (Dir);END IF;END PROCESS;Q = CONV_STD_LOGIC_VECTOR(Tmp
14、_Q,16); END Behavior;n MAX+PLUS II 1 Adder/Subtractor (16 Bit) 16 Registers 16 LEs+Registers+1 -1dirqrstclkCopyright 1997 Altera CorporationUsing Arithmetic Operators: Summaryn MAX+PLUS II VHDL Code Should Be Designed to Implement “Resource Sharing” Manually Compiler Does Not Do This for You Failure
15、 to Do This Results in Unwanted Complex Logic Impedes Both Fitting Instance NameEntity NameCopyright 1997 Altera CorporationThe Importance of Hierarchical Designsn Typical Customer Design StructureTop Level (Structural). . . . . . . . . . .Component 1 (Behavioral) Counters Adders State MachinesComponent 2 (Behavioral) Counters Adders State MachinesComponent n (Behavioral) Counters Adders State MachinesCopyright 1997 Altera CorporationThe Importance of Hierarchical Designsn Typical Customer Design Structure Is Inflexible Individual Compiler Options
