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1、High-Performance Digital Media Processor (TMS320DM642) 500-, 600-MHz Clock Rate Eight 32-Bit Instructions/Cycle 4000, 4800 MIPS Fully Software-Compatible With C64x.TMS320DM642VelociTI.2. Extensions to VelociTI. Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x. DSP Core Eight Highly Independent
2、Functional Units With VelociTI.2. Extensions: Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle Two Multipliers Support Four 16 x 16- Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
3、 Load-Store Architecture WithNon-Aligned Support 64 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions ConditionalInstruction Set Features Byte-Addressable (8-/16-/32-/64-Bit Data) 8-Bit Overflow Protection Bit-Field Extract, Set, Clear Normalization, Saturation,
4、 Bit-Counting VelociTI.2. Increased Orthogonality2级CACHE数量不同与 TMS320C6416L1/L2 Memory Architecture 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)C64X DSP 核
5、心64-Bit External Memory Interface (EMIF) Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) 1024M-Byte Total Addressable External Memory Space外挂存储器极限空间比DAM6416小10/100 Mb/s Ethernet MAC (EMAC) IEEE 802.3 Compliant Media Independen
6、t Interface (MII) 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels直接以太网集成Three Configurable Video Ports Providing a Glueless I/F to Common Video Decoder and Encoder Devices Supports Multiple Resolutions and Standards Supports RAW Video I/O Transport Stream Interface Mode直接图象接口不同 与
7、TMS320C6416VCXO Interpolated Control Port (VIC) Supports Audio/Video SynchronizationHost-Port Interface (HPI) 32-/16-Bit32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2主机接口与 MS320C6416 相同，速度快图象接口的细节Three Configurable Video Ports Pr
8、oviding a Glueless I/F to Common Video Decoder and Encoder Devices Supports Multiple Resolutions and Standards Supports RAW Video I/O Transport Stream Interface Mode图象接口的细节Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)Management Data Input/Output (MDIO)单独与 TMS320C6416 的多通道
9、音频串口Multichannel Audio Serial Port (McASP) Eight Serial Data Pins Wide Variety of I2S and Similar Bit Stream Format Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 FormatsInter-Integrated Circuit (I2C) BusThree 32-Bit General-Purpose TimersFlexible PLL Clock Gener
10、atorSixteen General-Purpose I/O (GPIO) Pins多通道音频串口Two Multichannel Buffered Serial PortsIEEE-1149.1 (JTAG) Boundary-Scan-Compatible 548-Pin Ball Grid Array (BGA) Package (GDK Suffix), 0.8-mm Ball Pitch 548-Pin Ball Grid Array (BGA) Package (GNZ Suffix), 1.0-mm Ball Pitch 0.13-m/6-Level Cu Metal Proc
11、ess (CMOS) 3.3-V I/Os, 1.2-V Internal (-500) 3.3-V I/Os, 1.4-V Internal (-600)多通道串口MIPS1200-24004800-8800Code size reductionAdvanced instruction packingImagingGeneralSpecial purpose instructionsCommunicationsGeneralSpecial purpose instructions8-bit MMACs300-60016-bit MMACs300-6008x 16x2400-44004800-
12、8800 8x 15x 25%MHz150-300 600-1100VelociTITM C62xTMVelociTI.2TM C64xTMImprovement4x 4xOverall PerformanceTMS320DM642 (DM642) device is based on the second-generation high- performance, advanced VelociTI. very-long-instruction-word (VLIW) architecture (VelociTI.2.) developed by Texas Instruments (TI)
13、, making these DSPs an excellent choice for digital media applications. 一代、二代的差别10X类类型格式分辨率帧频帧频 HZbit/像素比特率Mb/s电视电话电视电话QCIF176*14429.97129.1会议电视议电视CIF352*28829.971236.4常规电视规电视ITU-R601720*5762516165.9HDTVITU-R7091920*11522516884.7类类型带宽带宽 KHZ采样样率KHZ比特/样样点比特率kb/s 电话语电话语 音0.23.481296 宽带语宽带语 音0.057161422
14、4 调频调频 广播0.02153216512 CD光盘盘0.012044.116705.6 DAB/DAT0.01204816768 图像压缩的必要性语音压缩的必要性nxDSL modemsnPooled modems、3G基站n无线以太网n企业交换机 PBX,ATMn多路语音识别n多媒体网关n网络摄像机n安全认证n二维或三维条形码识别n高速打印机n网络设备开发平台n图像实时监控n图像采集、压缩、视频输出n高速实时数据采集与处理n雷达信号处理n软件无线电n医疗设备视频监控顶置盒Medical ImagingThe DM642 DSP possesses the perational flexi
15、bility of high- speed controllers and the numerical capability of array processors. 适合的应用The DM642 can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The 速度计算关系The Level 1 program
16、 cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. 第一级CACHE直接MAPThe Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. 第二级CACHE可以灵活配置The peripheral set includes: three configurable video
