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1、嵌入式系统原理内容概要嵌入式系统概述ARM7体系结构ARM7TDMI(-S)指令系统LPC2000系列ARM硬件结构嵌入式系统嵌入到对象体系中的专用计算机应用系统嵌入式系统的特点嵌入性、内含计算机、专用性嵌入式系统概述Embedded System devices used to control, monitor, or assist the operation of equipment, machinery or plants嵌入式系统组成嵌入式系统组成嵌入式系统通常由嵌入式处理器、外围设备、 嵌入式操作系统和应用软件等几大部分组成。在硬件上，嵌入式系统至少拥有一个高性能处 理器作为硬件平台
2、（目前以32位处理器为主流 ），如ARM、MIPS等处理器。在软件上，嵌入式系统拥有一个多任务操作系 统为软件系统平台，如Linux、WinCE、c/os- II、VxWorks、 palm OS、Windows Mobile 、Symbian等。嵌入式处处理器的分类类嵌入式微处理器(Embedded Microprocessor Unit, EMPU)嵌入式微控制器(Microcontroller Unit, MCU)嵌入式DSP处理器(Digital Signal Processor, DSP)嵌入式片上系统（SOC, System on Chip）Embeded System Techn
3、ologyARM体系结结构ARM7体系结构About the ARM architectureThe ARM is a Reduced Instruction Set Computer (RISC), as it incorporates these typical RISC architecture features: a large uniform register file a load/store architecture, where data-processing operations only operate on register contents, not directly
4、on memory contents simple addressing modes, with all load/store addresses being determined from register contents and instruction fields only uniform and fixed-length instruction fields, to simplify instruction decode. About the ARM architectureIn addition, the ARM architecture gives you: control ov
5、er both the Arithmetic Logic Unit (ALU) and shifter in every data-processing instruction to maximize the use of an ALU and a shifter auto-increment and auto-decrement addressing modes to optimize program loops Load and Store Multiple instructions to maximize data throughput conditional execution of
6、all instructions to maximize execution throughput. About the ARM architectureThree stage instruction pipelineProcessor operating statesThe ARM7TDMI-S processor has two operating states:ARM state 32-bit,word-aligned ARM instructions are executed in this stateThumb state 16-bit,halfword-aligned Thumb
7、instructionsOperating modesThe ARM7TDMI-S processor has seven operating modes:User mode is the usual ARM program execution state, and is used for executing most application programs. Fast interrupt (FIQ) mode supports a data transfer or channel process.Operating modesInterrupt (IRQ) mode is used for
8、 general- purpose interrupt handling. Supervisor mode is a protected mode for the operating system. Abort mode is entered after a data or instruction prefetch abort. System mode is a privileged user mode for the operating system. Operating modesUndefined mode is entered when an undefined instruction
9、 is executed. Modes other than User mode are collectively known as privileged modes. Privileged modes are used to service interrupts, exceptions, or access protected resources. Registers The ARM7TDMI-S processor has a total of 37 registers: 31 general-purpose 32-bit registers 6 status registers. The
10、se registers are not all accessible at the same time. The processor state and operating mode determine which registers are available to the programmer. The program status registerThe Mode bitsException vectorsException prioritiesEntering an exceptionR14_ = return link SPSR_ = CPSR CPSR4:0 = exceptio
11、n mode number CPSR5 = 0 /*Execute in ARM state*/ If = Reset or FIQ thenCPSR6 = 1 /*Disable fast interrupts*/*else CPSR6 is unchanged*/ CPSR7 = 1 /*Disable normal interrupts*/ PC = exception victor addressException HandleEntering ExceptionException HandleExit ExceptionException HandlingException entr
12、y/exit summaryLeaving an exceptionARM7TDMI(-S)指令系统Instruction syntaxS,寻寻址方式1 寄存器寻址2 立即寻址3 寄存器移位寻址4 寄存器间接寻址5 基址寻址6 多寄存器寻址7 堆栈寻址8 相对寻址灵活的第二操作数LDR Rd,Rn 零偏移LDR Rd,Rn,#0x04! 前索引偏移LDR Rd,Rn,#-0x04 前索引偏移LDR Rd,Rn,#0x04 后索引偏移LDR Rd,label 程序相对偏移(1)(2)(3)(4);子程序：使能IRQ中断Enable_IRQMRS R0, CPSRBIC R0, R0,#0x80MSR CPSR_c,R0MOV PC,LR ;子程序：禁能IRQ中断Disable_IRQMRS R0 CPSRORR R0, R0,#0x80 MSR CPSR_c,R0 MOV PC,LR 1.将CPSR寄存器内容读出到 R0；2.修改对应于CPSR中的I控 制位；3.将修改后的值写回 CPSR寄 存器的对应控制域；4.返回上一层函数；思考与练习?LPC2000系列ARM硬件结构刘永平 School of Computer Science & Technology, Xian Institute of Posts and Telecommunications, Xian
