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1、ARM Instruction Set a comment ADR r4,d LDR r1,r4 SUB r0,r0,r1 ; commentARM指令的一般编码格式cond00XopcodeSRnRdShifter-operand31 28 27 26 25 24 21 20 19 16 15 12 11 0opcode: 指令操作符编码 cond: 指令执行条件编码 S: 指令的操作是否影响CPSR的值 Rn: 包含第一个操作数的寄存器编码 Rd: 目标寄存器编码 Shifter_operand: 第二个操作数符号表示： , , ARM Addressing Modes (prelimin
2、ary)n寄存器寻址n例：ADD R0 , R1 , R2 ; (R1)+(R2)R0n立即数寻址n例：ADD R3 , R3 , #2 ; (R3)+2R3n寄存器间接寻址n例：LDR R0 , R3 ; (R3)R0n寄存器变址n例：LDR R0 , R1, #4 ; (R1)+4)R0n相对寻址n例：B rel ; (PC)+offsetPCPseudo-opsnSome assembler directives dont correspond directly to instructions:nDefine current address.nReserve storage.nConst
3、ants.ARM programming modelr0 r1 r2 r3 r4 r5 r6 r7r8 r9 r10 r11 r12 r13 r14 r15 (PC)CPSR310N Z C VARM status bitsnEvery arithmetic, logical, or shifting operation sets CPSR bits:nN (negative), Z (zero), C (carry), V (overflow).nExamples: n-1 + 1 = 0: NZCV = 0110.n231-1+1 = -231: NZCV = 0101.ARM data
4、typesnWord is 32 bits long.nWord can be divided into four 8-bit bytes.nARM addresses can be 32 bits long.nAddress refers to byte.nAddress 4 starts at byte 4.nCan be configured at power-up as either little- or big-endian mode.Instructions OverviewnData instructionsnLoad/Store instructionsnMove Instru
5、ctionsnComparison instructionsnBranch instructionsARM data instructionsnBasic format: ADD r0,r1,r2nComputes r1+r2, stores in r0.nImmediate operand: ADD r0,r1,#2nComputes r1+2, stores in r0.ARM data instructionsnADD, ADC : add (w. carry)nSUB, SBC : subtract (w. carry)nRSB, RSC : reverse subtract (w.
6、carry)nMUL, MLA : multiply (and accumulate)nAND, ORR, EORnBIC : bit clearnLSL, LSR : logical shift left/rightnASL, ASR : arithmetic shift left/rightnROR : rotate rightnRRX : rotate right extended with CData operation varietiesnLogical shift:nfills with zeroes.nArithmetic shift:nfills with zeroes or
7、ones.nRRX performs 33-bit rotate, including C bit from CPSR above sign bit.ARM load/store instructionsnLDR, LDRH, LDRB : load (half-word, byte)nSTR, STRH, STRB : store (half-word, byte)nAddressing modes:nregister indirect : LDR r0,r1nwith second register : LDR r0,r1,-r2nwith constant : LDR r0,r1,#4A
8、RM ADR pseudo-opnCannot refer to an address directly in an instruction.nGenerate value by performing arithmetic on PC.nADR pseudo-op generates instruction required to calculate address: ADR r1,FOO伪指令nADRnADRcond register, exprn将基于PC的地址值或基于寄存器的地址值读取到寄存器中 n汇编替换成一条指令nADRLnADRLcond register, exprnADRL伪指
9、令比ADR读取更大的地址范围。n汇编替换为两条指令nLDRnLDRcond register, =expr | label_exprn将一个32位的常数或地址值读取到寄存器中nNOPn空操作，如MOV R0, R0ARM move instructionsnMOV, MVN : move (negated)MOV r0, r1 ; r0 = b, branch to false blockIf statement, contd.; true block MOV r0,#5 ; generate value for x ADR r4,x ; get address for x STR r0,r4
10、 ; store x ADR r4,c ; get address for c LDR r0,r4 ; get value of c ADR r4,d ; get address for d LDR r1,r4 ; get value of d ADD r0,r0,r1 ; compute y ADR r4,y ; get address for y STR r0,r4 ; store y B after ; branch around false blockIf statement, contd.; false block fblock ADR r4,c ; get address for
11、c LDR r0,r4 ; get value of c ADR r4,d ; get address for d LDR r1,r4 ; get value for d SUB r0,r0,r1 ; compute a-b ADR r4,x ; get address for x STR r0,r4 ; store value of x after .Example: Conditional instruction implementation; true block MOVLT r0,#5 ; generate value for x ADRLT r4,x ; get address fo
12、r x STRLT r0,r4 ; store x ADRLT r4,c ; get address for c LDRLT r0,r4 ; get value of c ADRLT r4,d ; get address for d LDRLT r1,r4 ; get value of d ADDLT r0,r0,r1 ; compute y ADRLT r4,y ; get address for y STRLT r0,r4 ; store yExample: switch statementnC: switch (test) case 0: break; case 1: nAssemble
13、r: ADR r2,test ; get address for test LDR r0,r2 ; load value for test ADR r1,switchtab ; load address for switch table LDR r15,r1,r0,LSL #2 ; index switch table switchtab DCD case0 DCD case1 .Example: FIR filternC:for (i=0, f=0; iN; i+) f = f + ci*xi;nAssembler; loop initiation code MOV r0,#0 ; use
14、r0 for I MOV r8,#0 ; use separate index for arrays ADR r2,N ; get address for N LDR r1,r2 ; get value of N MOV r2,#0 ; use r2 for fFIR filter, cont.dADR r3,c ; load r3 with base of c ADR r5,x ; load r5 with base of x ; loop body loop LDR r4,r3,r8 ; get ci LDR r6,r5,r8 ; get xi MUL r4,r4,r6 ; compute
15、 ci*xi ADD r2,r2,r4 ; add into running sum ADD r8,r8,#4 ; add one word offset to array index ADD r0,r0,#1 ; add 1 to i CMP r0,r1 ; exit? BLT loop ; if i N, continueARM subroutine linkagenBranch and link instruction: BL foonCopies current PC to r14.nTo return from subroutine: MOV r15,r14Nested subroutine callsnNesting/recursion requires coding convention:f1LDR r0,r13 ; load arg into r0 from stack ; call f2() STR r13!,r14 ; store f1s return adrs STR r13!,r0 ; store arg to f2 on stack BL f2 ; branch and link to f2 ; return from f1() SUB r13,#4 ; pop f2s arg off stack LDR r1
