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1、?IP? ?Rick Kelly?Synopsys?2009?1? ?Soc? ? ? ? ?CDC?Synopsys DesignWare? ?CDC? ? ? ?DesignWare? ? DW_sync ? DW_pulse_sync, DW_pulseack_sync ? DW_data_sync, DW_data_sync_na, DW_data_sync_1c ? DW_fifo_s2_sf, DW_fifo_2c_df, DW_stream_sync ? DW_reset_sync ? DW_data_qsync_hl, DW_data_qsync_lh ? ? ?1? ?0?1
2、? ? ?1?0? ?2? Clock to Q delay ?Q? FF Minimum specs ? ?2? ? ? ? ?Clk_d? ? ? ?Clk_d? ? ? ? ? ? ? ?Q? ? ? ? ?MTBF? ? ? fclk ? fdata ? tres ? T0?T1? ? ? ? ?2? ? ?2?FF1?Q?FF2? ? ?MTBF? ?FPGA?3?1?FF2? ?2?3? Sampe MTBF test MTBF? Error Counter ? ?3? ? 3? T0?T1?4? ? ?MTBF? ? ?T0?T1? ?MTBF? ?4? ? ? ?MTBF? ?
3、Debora Grosse, Unisys, EDN, 1994 http:/ ?Kleeman end for; ?verif_en = 0?1? verif_en?32?verif_en = 1?DW_sync? verif_en? 0 1 2 ? ?_sync_type ?_sync_type to ?_sync_type + 1 ?_sync_type to ?_sync_type + 3 ?1 verif_en? ?_sync_type?f_sync_type ?r_sync_type? Width? Width? To ?1? Random ? Random ? ?32 ?veri
4、f_en = 1?DW_sync? ?DW_data_sync_1c ?verif_en = 2?DesignWare Library CDC?3 ?33?4? 2?3? Width? Width? To ?1? Random ? Random ? ?33 ?verif_en = 2?DW_sync? DW_sync? ? DW_ sync? ?34? Source ? Destination ? 1st ?1? 2nd ?2? Intermediate? Intermediate? ?34 ? ? ?MTBF? ?CDC ?DW_sync? ?DW_sync?50%?CDC? DW_sync
5、?CDC? ? ?CDC? ?Design Compiler? ? ? ?DesignCompiler?B-2008.09?DesignWare CDC? ?synlib_preferred_ffs? DC? ?FFSYNCFD1?FFSYNCFD2? ? set synlib_preferred_ffs “FFSYNCFD1 FFSYNCFD2” ?DC?Tcl? ?B-2008.09?Design Compiler?Tcl?DW_sync? ? DesignWare CDC? DesignWare Library?CDC? ? DW_sync ? DW_pulse_sync, DW_pul
6、seack_sync ? DW_data_sync, DW_data_sync_na, DW_data_sync_1c ?DW_fifo_s2_sf, DW_fifo_2c_df, DW_stream_sync ? DW_reset_sync ? DW_data_qsync_hl, DW_data_qsync_lh ? ?IP? ?Synopsys DesignWare Library CDC IP? IP ?IP? Information link? ?35 DesignWare Library? ?35? ? ?A?ack_delay=0? ?DW_data_sync? ? ? ? ? ? ?DW_data_sync?ack_delay?r_sync_type ?2? Synchronization .?ack_delay=0, r_sync_type=2?clk_s? Internal ? Internal data to capture:? New data? Ack ?clk_s?clk_d? Second ?
