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1、 2009 Altera Corporation 1QuartusII Software Design Series: Timing AnalysisQuartusII Software Design Series: Timing Analysis- Timing analysis basics- Timing analysis basics 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Cor
2、poration 2ObjectivesObjectivesnDisplay a complete understanding of timing analysis 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 3How does timing verification work?How does timing verification work?nEvery devic
3、e path in design must be analyzed with respect to timing specifications/requirements-Catch timing-related errors faster and easier than gate-level simulation typically 1 cycle) 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera
4、 Corporation 7Setup Th Trem -External device & board timing parameters may be needed (Ex. 1)ASSPreg1PRE D QCLRFPGA/CPLDreg2PRE D QCLROSCFPGA/CPLDreg1PRE D QCLRreg2PRE D QCLRExample 1Example 2Data arrival pathData arrival pathData required pathData required path 2009 Altera CorporationAltera, Stratix
5、, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 19Why Are These Calculations Important?Why Are These Calculations Important?nCalculations are important when timing violations occur-Need to be able to understand cause of violationnExample causes-Data
6、path too long-Requirement too short (incorrect analysis)-Large clock skew signifying a gated clock, etc.nTimeQuest timing analyzer uses them-Equations to calculate slack-Terminology (launch and latch edges, Data Arrival Path, Data Required Path, etc.) in timing reports 2009 Altera CorporationAltera,
7、 Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 20Timing Models in DetailTiming Models in DetailnQuartus II software models device timing at two PVT conditions by default-Slow Corner ModellIndicates slowest possible performance for any single
8、 pathlTiming for slowest device at maximum operating temperature and VCCMIN-Fast Corner ModellIndicates fastest possible performance for any single pathlTiming for fastest device at minimum operating temperature and VCCMAXnWhy two corner timing models?-Ensure setup timing is met in slow model-Ensure
9、 hold timing is met in fast modellEssential for source synchronous interfacesnThird model (slow, min. temp.) available only for 65 nm and smaller technology devices (temperature inversion phenomenon) 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore a
10、re trademarks of Altera Corporation 21Generating Fast/Slow NetlistGenerating Fast/Slow NetlistnSpecify one of the default timing models to be used when creating your netlistnDefault is the slow timing netlistnTo specify fast timing netlist-Use -fast_model option with create_timing_netlist command-Ch
11、oose Fast corner in GUI when executing Create Timing Netlist from Netlist menu-CANNOT select fast corner from Tasks Pane 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 22Specifying Operating Conditions Specifyin
12、g Operating Conditions nPerform timing analysis for different delay models without recreating the existing timing netlistnTakes precedence over already generated netlistnRequired for selecting slow, min. temp. model and other models (industrial, military, etc.) depending on devicenUse get_available_
13、operating_conditionsto see available conditions for target device 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera CorporationReference DocumentsReference DocumentsnQuartus II Handbook, Volume 3, Chapter 7 The Quartus II Time
14、Quest Timing Analyzer http:/ Start Tutorial http:/ _cookbook.pdf 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera CorporationReference DocumentsReference DocumentsnSDC and TimeQuest API Reference Manual-http:/ dfnAN 481: Appl
15、ying Multicycle Exceptions in the TimeQuest Timing Analyzer-http:/ 433: Constraining and Analyzing Source- Synchronous Interfaces-http:/ 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 25Instructor-Led TrainingWith Alteras instructor-led training courses, you can:Listen to a lecture from an Altera technical training engineer (instructor) Complete han
