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1、Figures 16 and 17 show timing diagrams for interfacing to the AD7705/AD7706 with CS used to decode the part. Figure 16 is for a read operation from the AD7705/AD7706s output shift register while Figure 17 shows a write operation to the input shift register. It is possible to read the same data twice
2、 from the output register even though the DRDY line returns high after the first read operation. Care must be taken, however, to ensure that the read operations have been completed before the next output update is about to take place. 图 16 和 17 显示了用于连接的时序图 与 CS AD7705/AD7706 的用于解码的一部分。图 16 为从 AD7705
3、/AD7706 的的输出转变读操作 而图 17 显示寄存器写操作的输入 移位寄存器。它可以读取相同的数据两次 输出寄存器即使 DRDY 线后返回高 第一个读操作。必须注意，但是，为了确保 的读操作完成后，下一 输出更新即将发生。The AD7705/AD7706 serial interface can operate in three-wire mode by tying the CS input low. In this case, the SCLK, DIN and DOUT lines are used to communicate with the AD7705/ AD7706 an
4、d the status of DRDY can be obtained by interrogat- ing the MSB of the Communications Register. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port bit. For microcontroller interfaces, it is recommended that the SCLK id
5、les high between data transfers. 该 AD7705/AD7706 的串行接口可以工作在三线 模式通过把 CS 输入低。在这种情况下，在 SCLK，德国 DIN 标准 和 DOUT 线用于通信与 AD7705 的/ AD7706 则和 DRDY 的状态可以得到 interrogat- 荷兰国际集团的通信 MSB 寄存器。这个计划是 适合用于连接微控制器。如果 CS 是需要作为 解码信号，它可以由一个端口位。对于 微控制器接口，因此建议在 SCLK 空闲之间的数据传输高。The AD7705/AD7706 can also be operated with CS u
6、sed as a frame synchronization signal. This scheme is suitable for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS since CS would normally occur after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers provided the timing numbers
7、are obeyed. 该 AD7705/AD7706 的营办，也可以用来作为政务司司长 帧同步信号。这项计划是合适的 DSP 接口。在这种情况下，第一个位（MSB）是有效的时钟 由 CS 了，因为政务司司长后，通常会出现的下降沿 在 DSP 的 SCLK 的。在 SCLK 之间可以继续运行 数据传输所提供的时序数是服从。The serial interface can be reset by exercising the RESET input on the part. It can also be reset by writing a series of 1s on the DIN inp
8、ut. If a Logic 1 is written to the AD7705/AD7706 DIN line for at least 32 serial clock cycles the serial interface is reset.This ensures that in three-wire systems, if the interface gets lost either via a software error or by some glitch in the system, it can be reset back to a known state. This sta
9、te returns the interface to where the AD7705/AD7706 is expecting a write operation to its Communications Register. This operation in itself does not reset the contents of any registers but since the interface was lost, the information written to any of the registers is unknown and it is advisable to
10、 set up all registers again. 该串行接口可行使的 RESET 复位输入 在零件上。它也可以书面将其复位 1 秒的 A 系列 符合 DIN 输入。如果一个逻辑 1 被写入 AD7705/AD7706 的符合 DIN 在至少 32 个串行时钟周期的串行接口线复位。 这确保了在三线系统中，如果丢失的接口 无论是通过一个软件错误或系统故障中的一些，它可以 复位回到已知状态。这种状态返回接口 到那里的 AD7705/AD7706 的期待写操作 其通信寄存器。这本身操作不 复位所有寄存器的内容，但由于界面 丢失，写入任何寄存器的信息是：未知 而且最好是重新设置所有的寄存器。So
11、me microprocessor or microcontroller serial interfaces have a single serial data line. In this case, it is possible to connect the AD7705/AD7706s DATA OUT and DATA IN lines together and connect them to the single data line of the processor. A 10 k pull-up resistor should be used on this single data
12、line. In this case, if the interface gets lost, because the read and write operations share the same line the procedure to reset it back to a known state is somewhat different than previously described. It requires a read operation of 24 serial clocks followed by a write operation where a Logic 1 is
13、 written for at least 32 serial clock cycles to ensure that the serial interface is back into a known state. 有些微处理器或微控制器的串行接口有 单线串行数据。在这种情况下，它可以连接 AD7705/AD7706 的S 在 OUT 和数据线数据一起 并将它们连接到处理器的单根数据线。一10k 的上拉电阻时，必须使用这个单一的数据线。在 这种情况下，如果接口丢失，因为读取和写入 业务共享同一行的程序，重置回 已知的状态比以前有所不同的描述。这 需要 24 串行时钟读取操作后跟一个写 逻辑 1 的运作情况，至少是 32 个串行时钟书面 周期，以确保串行接口是回一个已知 状态。
