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1、 EEPROM Features Write Protect Pin for Hardware Data Protection Utilizes Different Array Protection Compared to the AT24C02/04/08/16 Low-voltage and Standard-voltage Operation2.7(VCC =2.7Vto5.5V)1.8(VCC =1.8Vto5.5V) InternallyOrganized256x8(2K),512x8(4K),1024x8(8K)or2048x8(16K) 2-wire Serial Interfa
2、ce Schmitt Trigger, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate for AT24C02A, 04A and 08A 100 kHz (1.8V) and 400 kHz (2.5V, 2.7V and 5V) Clock Rate for AT24C16A 8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write M
3、odes Partial Page Writes are Allowed Self-timed Write Cycle (10 ms max) High Reliability Endurance: One Million Write Cycles Data Retention: 100 Years Automotive Grade and Extended Temperature Devices Available 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP PackagesDescriptionThe AT24C0
4、2A/04A/08A/16A provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation ar
5、e essential. The AT24C02A/04A/08A/16A is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.Pin Description S
6、ERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into eachEEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain
7、 or open collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that must be hard wired for the AT24C02A. As many as eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section)
8、.The AT24C04A uses the A2 and A1 inputs for hard wire addressing and a total of four4K devices may be addressed on a single bus system. The A0 pin is a no-connect.WRITE PROTECT (WP): The AT24C02A/04A/08A/16A have a Write Protect pin that provides hardware data protection. The Write Protect pin allow
9、s normal read/write operations when connected to ground (GND). When the Write Protect pin is connected toVCC, the write protection feature is enabled and operates as shown in the following table.Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.
10、Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a startor stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede
11、 any other command (refer to Start and Stop Definition timing diagram).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLED
12、GE: All addresses and data words are serially transmitted to and fromtheEEPROMin8bitwords.The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C02A/04A/08A/16A features a low power standby mode which is enabled: (a) up
13、on power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while
14、SCL is high and then (c) create a start condition as SDA is high.Device AddressingThe 2K, 4K and 8K EEPROM devices all require an 8 bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1).The device address word consists of a mandatory
15、 one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins.The 4K EEPROM only uses the A2 and A1 de
16、vice address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hard-wired input pins. The A0 pin is no-connect.The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no-connect.The 16K EEPROM does not use the device address pins, which limits
