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1、ZYNQ平台架构及配置,目录,一、 ZYNQ平台的硬件架构二、 AXI 协议三、 ZYNQ的部分可重构配置,ZYNQ平台的硬件架构,背景简介,背景简介,ZYNQ7000系列ARM+FPGA结构,XILINX传统FPGA的局限性？,ZYNQ平台的硬件架构,架构：1、PS（处理器系统）（流程控制等串行设计） 2、PL（可编程逻辑）（并行算法设计）,ZYNQ平台的硬件架构,PS由四块组成：1、APU(应用处理单元)2、内存接口3、IO外设（USB2.0、Ethernet、CAN、SPI、UART、IIC、SD/SDIO、GPIO）4、互连线（APU、IOP和内存单元相互连接，并通过一个多层的AXI互
2、连线与PL连接）,ZYNQ平台的硬件架构,APU结构1、ACP2、SCU3、Cortex-A9(x2)4、L1 32KB（I/D） 共享L2 512KB,ZYNQ平台的硬件架构,内存接口,ZYNQ平台的硬件架构,IO外设 RGMII接口,ZYNQ平台的硬件架构,AXI总线架构AXI_HP 用于PL的四个高性能、高带宽主接口，位宽可配64/32，可访问PS的DDR3控制器和PS的片上RAM资源AXI_GP四个通用接口（两主两从），每个位宽32，可访问PS的DDR3控制器，PS片上RAM资源和其他从设备AXI_ACP用于PL的一个加速一致性主端口，提供快速访问CPU，可选的L1或L2缓存一致性,Z
3、YNQ平台的硬件架构,PL组成：1、可配置逻辑块(CLB)2、36KB块BRAM3、数字信号处理DSP48E1 Slice4、可编程IO5、时钟管理6、XADC,ZYNQ平台的硬件架构,可编程IO,ZYNQ平台的硬件架构,XADC模块,XADC模块,ZYNQ平台的硬件架构,ZYNQ平台的硬件架构,AXI协议,AXI4.0是ARM公司提出的AMBA 3.0协议的升级版，是一种高性能、高带宽、低延迟的片内总线。,AXI协议,AXI协议具有如下特点：总线的地址/控制和数据通道是分离的；支持不对齐的数据传输；在突发传输中，只需要首地址；同时具有分离读/写数据通道；更加容易进行时序收敛。,通道介绍,AX
4、I接口具有5个独立通道：写地址通道（Write address channel，AW）；写数据通道（Write data channel，W）；写响应通道（Write response channel，B）；读地址通道（Read address channel，AR）；读数据通道（Read data channel，R）；每个通道都是一个独立的AXI握手协议。,READY/VALID握手机制,每个通道都有一对VALID/READY信号发送方用VALID指示什么时候数据或控制信息是有效的；接收方用READY指示可以接收数据或控制信息。传输发生在VALID和READY信号同时为高的时候。通道之间的
5、关系：各个通道都可以独立握手，相互之间的关系是灵活的；读数据必须总是跟在与其数据相关联的地址之后；写响应必须总是跟在与其相关联的写交易的最后出现。,READY/VALID握手机制,读交易中的握手之间的依赖关系,写交易中的握手之间的依赖关系,读交易过程,写交易过程,读猝发交易,读猝发交易过程中典型信号的交互过程,写猝发交易,写猝发交易过程中典型信号的交互过程,重叠猝发交易,重叠猝发交易过程中典型信号的交互过程,AXI 互联,AXI互联结构模型包括：直通模式只转换模式N-1 互联模式1-N 互联模式N-M 互联模式,互联模式,直通模式,只转换模式,N-1互联模式,1-N互联模式,N-M互联模式,共
6、享写和读地址仲裁结构,N-M互联模式,稀疏互联写和读数据通道,Partial Reconfiguration in Zynq,Based on modulesBased on diversities,Partial Reconfiguration in Zynq,What Problems Does It Solve?System cost, size, and power constraints Multiplex hardware functions Evolving protocol and industry standards Reprogramability as standards
7、 evolve Mission critical uptime Update on the fly while system still running Long design implementation cycle times Accelerate development with focus on reconfigurable partition,Some Terminology,Reconfigurable Partition (RP) The physical location of FPGA resources selected for partial reconfiguratio
8、n Static logic Everything but the RP(s) The part of the design that doesnt change Reconfigurable Module (RM) Logic that lives in the RP Defined by hardware interfaces and ports Functional variants for associated RP Different protocol, task, filter, etc.,Design Flow,Structure the design Separate func
9、tions into hierarchical blocks Identify functions to be made into partitions Identify set of signals that will become RP interface,Design Flow, Synthesize Bottom-up Static “top” and RMs synthesized seperately,Design Flow,Assemble static design with RM variants RMs replace black boxes in static “top”
10、,Design Flow,Floorplan the RPs and run DRCs Define regions and logic resources to be included,Design Flow,Implementation Configurations for static logic and all reconfigurable modules Repeat for all modules,Design Flow,Verify all configurations Ensure that static portions match identically,Design Co
11、nsiderations,Vivado stores design data in checkpoints Save full design as a configuration checkpoint for bitstream creation RMs can also be stored as their own checkpoints Save static-only checkpoint to be reused across multiple configurations Routed static checkpoint can remain open in memory Resul
12、ts are locked at the routing level,Design Considerations,Design Considerations,Partition Pins are junctions between static and reconfigured logic Interface wires can be broken at interconnect tile site Anchor mid-route between static and reconfigurable logic No overhead at reconfigurable partition interface,Design Considerations,Not Everything Can Be Reconfigured,Components CANNOT be reconfigured Clocking resources BUFG, BUFR, MMCM, PLL, etc. I/O resources ISERDES, OSERDES, IDELAYCTRL, etc. MGTs and related components,
