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1、XAPP687 (v1.0) November 21, 2003 11-800-255-7778 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http:/ All other trademarks and registered trademarks are the property of their respective owners. All specificatio
2、ns are subject to change without notice.NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information as is. By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation i
3、s free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that thi
4、s implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.Summary This application note describes the encoding and decoding blocks of the 64B/66B encoding scheme. This application allows designs to use the RocketIO transcei
5、ver of the Virtex-II Pro device or an external SerDes with either Virtex-II or Virtex-II Pro devices.Introduction Serial standards use an embedded clock in the data stream. To ensure the Clock Data Recovery (CDR) can track the embedded clock; a transition rich data stream is required. In the past, 8
6、B/10B encoding provided the transition rich data along with a DC balanced data stream for many standards, including 1X and 2X Fibre Channel and Gigabit Ethernet. However, as serial rates increase to 3.125 Gbits/s and greater, the overhead of 8B/10B encoding becomes unacceptable in standards such as
7、10G Fibre Channel and 10G Gigabit Ethernet.To reduce the overhead, 64B/66B encoding was created. This scheme encodes 64 bits of data into 66 bits, providing a 3% overhead compared to the 20% overhead of 8B/10B encoding. Figure 1 shows how the 64B/66B encode/decode logic of this application fits in a
8、 complete system. This application note provides detailed information on the reference design indicated in grey. It does not cover the scrambler, descrambler, synchronization block, or gearbox. Their functions are briefly described after the figure.The 64B/66B encoder takes XGMII signals consisting
9、of a 64-bit data and a 8-bit control bus and converts them into 66-bit code words according to the scheme outlined in Section 49.2.4 of the IEEE 802.3ae specification. The decoder converts the 66-bit code words back to XGMII-compatible signals.Application Note: Virtex-II and Virtex-II Pro DevicesXAP
10、P687 (v1.0) November 21, 200364B/66B Encoder/DecoderAuthor: Nick McKay and Matt DiPaoloRFigure 1: 64B/66B System Data Path64B/66BEncodeScramblerGearboxTXDTXCRXDXAPP687Reference DesignXGMIIInterfaceRXCDescrambler/SynchronizationBlockData WidthConversionData WidthConversion64B/66BDecodeSerDes646666666
11、616168648x687_01_1120032 XAPP687 (v1.0) November 21, 20031-800-255-7778Reference DesignRThe scrambler block encrypts the transmitted data, and the descrambler block decrypts the received data. These blocks are not required in all applications and are not included in the reference design.The synchro
12、nization block aligns the incoming serial data on a 66-bit boundary to also align on the 64-bit boundary on the XGMII side of the 64B/66B encode/decode block. This block is not included in the reference design. The gearbox creates the two clock domains to allow the 66 data bits to be converted into
13、the correct SerDes interface width. This design function requires a shift register and data width converter. This block is not included in the reference design due to the numerous bus interfaces available. Reference DesignThe reference design, which is available in VHDL or Verilog, consists of three
14、 modules: encoder, decoder, and encoder_decoder_top. The encoder_decoder_top module instantiates the encoder and decoder blocks along with other logic including clock generation. The VHDL reference design contains four files: encode_decode_top.vhd, encoder.vhd, decoder.vhd, and pcs_util.vhd. The Ver
15、ilog reference design contains three files: encode_decode_top.v, encoder.v, and decoder.v. The design files can be found on the following website: http:/ 2 shows a block diagram of the encoder.Figure 2: Encoder Block DiagramDATA_FIELDREG_TYPEREG_REG_TXDREG_REG_TXCREG_TXDREG_TXCXGMII_TXDXGMII_TXCTYPE
16、_FIELD_GENT_TYPESYNC_FIELDDATA_OUTTYPE_REGLANE DECODEBLOCK TYPE FIELDGENERATIONCODE GENERATIONREGISTERSREGISTERSSYNC_FIELD_GEN x687_02_1024030178648645682Reference DesignXAPP687 (v1.0) November 21, 2003 31-800-255-7778RTable 1 defines all encoder block signals. Figure 3 shows the encoding scheme, and Table 2 provides the valid control codes, taken from t
