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1、1,Digital Logic Design and ApplicationLecture #20,Chapter 8Sequential Logic Design Practices,UESTC, Spring 2013,2,Chapter 7 Sequential Logic Design Principles,Combinational logic circuit Outputs = f ( current inputs ) Sequential logic circuit Outputs = f ( current inputs + entire input history ),sto
2、red in memory elements Latches and Flip-Flops,feedback sequential circuit clocked synchronous state machine,3,Chapter 7 Sequential Logic Design Principles,Clock signal clock period, clock frequency, clock tick, duty cycle Bistable Elements Metastable Characteristic Latches S-R Latch, D Latch Flip-Fl
3、ops, F/F Edge-Triggered flip-flop Master/Slave flip-flop,D FF T FF J-K FF S-R FF,4,State-Machine Structure,Next State Logic F,State Memory,Output Logic G,inputs,outputs,excitation,current state,clock signal,5,State-Machine Analysis,Determine excitation equation for flip-flop control inputs Determine
4、 output equation from the circuit diagram Substitute the excitation equations into the flip-flop characteristic equations to obtain transition equations Use the transition equations and output equations to construct a transition/output table Name the states and obtain a state/output table (Optional)
5、 Draw a state diagram Describe the circuit function,6,State-Machine Design,Construct state/output table ( or state diagram ) (optional) State minimization State assignment Create transition/output table Derive transition equations and output equations Choose a flip-flop type for the state memory Con
6、struct excitation equations Draw a logic circuit diagram,7,State-Machine Design,State table transition table transition equation,State diagram transition list transition equation,Excitation equation, State assignment ,FF choose, K-map, (),(), (),(),Chapter 7 Sequential Logic Design Principles,Severa
7、l important conceptions Bi-stable / Latch Meta-stable enable Synchronous/ Asynchronous Finite state Logic function,8,9,Chapter 8Sequential Logic Design Practices,SSI Latches and Flip-Flops MSI Device: Counters, Shift Registers Others: Documents, Iterative, Failure and Metastability,10,8.1 Sequential
8、-Circuit Documentation Standards,General Requirements ( P680 ) Logic Symbols Edge-Triggered indicator, Master/Slave Output indicator asynchronous preset (at the Top) and clear (at the bottom) all inputs on the left, all outputs on the right State-Machine Description word descriptions, state tables,
9、state diagrams, transition lists Timing Diagrams and Specifications ( P682 ),11,hold-time margin,12,8.2 Latches and Flip-Flops,1. SSI Latches and Flip-Flops,13,2. Switch Debouncing,14,0,0,1,1,0,0,1,1,15,说明： 开关悬空后， SW_L会稍大于0电平 可在输出端加一级缓冲解决,开关切换时会出现瞬时短路现象，不应与高速 CMOS器件一起使用, 可采用锁存器结构。,16,3. Bus Holder C
10、ircuit,SDATA,17,4. Multibit Registers and Latches,4-bit register 74x175,18,8-bit (octal)register,74x374 ( 3-state output ),19,74x377 clock enable,74x273 asynchronous clear,74x374 output enable,other octal registers,20,74x377（Clock enable）,2-input Multiplexer,21,Register vs. Latch, whats the differen
11、ce? register: edge-triggered behavior latch: output follows input when C is asserted, Octal Latch,Octal register,22,8.4 Counters,Modulus: the number of states in the cycle A modulo-m counter, or a divide-by-m counter An n-bit binary counter,Any sequential circuit whose state diagram is a single cycl
12、e.,8.4 Counter,a modulo-2 counter,23,State assignment: S0: 0 S1: 1,S0,S1, 1-bit counter,Transition table S S* Z 0 1 0 1 0 1,0,1,Q0,Transition equation: Q0*=Q0,Q0*, Toggle, T F.F,CLK,One T F.F for one bit counter, N-bit counter?, use N F.F,24,1. Ripple Counters,0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
13、 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1,asynchronous counter,counter adder,Q3 Q2 Q1 Q0, Toggle, Toggle at Q0 , Toggle at Q1 , Toggle at Q2 ,In the worst case, the propagation delay of the MSB is ntTQ .,25,2. Synchronous Counters,在多位二进制数的末位加 1， 仅当第 i 位
14、以下的各位都为 1 时， 第 i 位的状态才会改变。 最低位的状态每次加1都要改变。,Using T flip-flop with enable:,Q* = ENQ + ENQ = EN Q,ENi = Qi-1Qi-2 Q1Q0,EN0 =1,Q* = D= EN Q,Di = (Qi-1 Q1 Q0) Qi,Using D flip-flop with enable,D0 = 1 Q0 = Q0,26,synchronous 4-bit binary up counter,1,如何加入使能端？,27,synchronous counter with serial enable logic,
15、28,synchronous counter with parallel enable logic,29,3. A 4-Bit Binary Counter 74x163,It uses D flip-flops internally to facilitate the load and clear functions.,With synchronous clear and load inputs,P714 Figure 8-28 internal logic diagram for the 74x163,30,Q0,Q1,Q2,Q3,D0,D1,D2,D3,(Qi-1 Q0),Qi coun
16、ting,32,synchronous clear input,0,0,0,0,33,synchronous load input,0,1,1,0,2-to-1 MUX,34,ENP and ENT enable inputs,clear “ripple carry out” signal,ripple carry out RCO=ENT QD QC QB QA,35,operate in a free-running mode,Free-running 16 Count if ENP andENT both asserted. Load if LD is asserted(overrides counting). Clear if CLR is asserted(overrides loading and counting). All operations take place on rising CLK edge. RCO is asserted if ENT is asserted and count = 15
