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1、HY57V561620 L T 4Banks x 4M x 16Bit Synchronous DRAM This document is a general product description and is subject to change without notice Hyundai Electronics does not assume any responsibility for use of circuits described No patent licenses are implied Revision 1 8 Apr 01 DESCRIPTION The HY57V561
2、620T is a 268 435 456bit CMOS Synchronous DRAM ideally suited for the main memory applications which require large memory density and high bandwidth HY57V561620 is organized as 4 banks of 4 194 304x16 The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock
3、 All inputs and outputs are synchronized with the rising edge of the clock input The data paths are internally pipelined to achieve very high bandwidth All input and output voltage levels are compatible with LVTTL Programmable options include the length of pipeline CAS latency of 2 or 3 the number o
4、f consecutive read or write cycles initiated by a single control command Burst length of 1 2 4 8 or full page and the burst count sequence sequential or interleave A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new b
5、urst read or write command on any cycle This pipelined design is not restricted by a 2N rule FEATURES Single 3 3V 0 3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP II with 0 8mm of pin pitch All inputs and outputs referenced to positive edge of sy
6、stem clock Data mask function by UDQM and LDQM Internal four banks operation Auto refresh and self refresh 8192 refresh cycles 64ms Programmable Burst Length and Burst Type 1 2 4 8 and Full Page for Sequential Burst 1 2 4 and 8 for Interleave Burst Programmable CAS Latency 2 3 Clocks ORDERING INFORM
7、ATION Part No Clock FrequencyPowerOrganizationInterfacePackage HY57V561620T HP133MHz Normal 4Banks x 4Mbits x16 LVTTL400mil 54pin TSOP II HY57V561620T H133MHz HY57V561620T 8125MHz HY57V561620T P100MHz HY57V561620T S100MHz HY57V561620LT HP133MHz Lower Power HY57V561620LT H133MHz HY57V561620LT 8125MHz
8、 HY57V561620LT P100MHz HY57V561620LT S100MHz HY57V561620 L T Revision 1 8 Apr 01 PIN CONFIGURATION VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49
9、 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10 AP A0 A1 A2 A3 VDD 54pin TSOP II 400mil x 875mil 0 8mm pin pitch PIN DESCRIPTION PINPIN NAMEDESCRIPTION CLKClock The system clock input All other
10、 inputs are registered to the SDRAM on the rising edge of CLK CKEClock Enable Controls internal clock signal and when deactivated the SDRAM will be one of the states among power down suspend or self refresh CSChip SelectEnables or disables all inputs except CLK CKE UDQM and LDQM BA0 BA1Bank Address
11、Selects bank to be activated during RAS activity Selects bank to be read written during CAS activity A0 A12Address Row Address RA0 RA12 Column Address CA0 CA8 Auto precharge flag A10 RAS CAS WE Row Address Strobe Col umn Address Strobe Write Enable RAS CAS and WE define the operation Refer function
12、truth table for details UDQM LDQMData Input Output MaskControls output buffers in read mode and masks input data in write mode DQ0 DQ15Data Input OutputMultiplexed data input output pin VDD VSSPower Supply GroundPower supply for internal circuits and input buffers VDDQ VSSQData Output Power GroundPo
13、wer supply for output buffers NCNo ConnectionNo connection HY57V561620 L T Revision 1 8 Apr 01 FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x16 I O Synchronous DRAM X decoders State Machine A0 A1 A12 BA0 BA1 Address buffers Address Register Mode Registers Row Pre Decoders Column Pre Decoders Column Add C
14、ounter Row Active Column Active Burst Counter Data Out Control CAS Latency Internal Row Counter DQ0 DQ1 DQ14 DQ15 Self Refresh Logic Timer Pipe Line Control I O Buffer Logic Bank Select Sense AMP I O Gate CLK CKE CS RAS CAS WE UDQM LDQM 4Mx16 Bank 3 X decoders Memory Cell Array Y decoders X decoders
15、 4Mx16 Bank 0 4Mx16 Bank 1 4Mx16 Bank 2 HY57V561620 L T Revision 1 8 Apr 01 ABSOLUTE MAXIMUM RATINGS Note Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION TA 0 to 70 C Note 1 All voltages are referenced to VSS 0V 2 VIH max is acceptable 5 6V A
16、C pulse width with 3ns of duration 3 VIL max is acceptable 2 0V AC pulse width with 3ns of duration AC OPERATING CONDITION TA 0 to 70 C VDD 3 3 0 3V VSS 0V Note 1 Output load to measure access time is equivalent to two TTL gates and one capacitor 50pF For details refer to AC DC output circuit ParameterSymbolRatingUnit Ambient TemperatureTA0 70 C Storage TemperatureTSTG 55 125 C Voltage on Any Pin relative to VSSVIN VOUT 1 0 4 6V Voltage on VDD relative to VSSVDD VDDQ 1 0 4 6V Short Circuit Outpu
