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1、Assignment 51. Analyze SE of Actel ACT (Figure 5.4(d) with any possible combinations of C1, C2 and CLR C controls. a. Which functions does SE support? b. Verify these functions by using Modelsim simulator at logic level or HSPICE circuit simulator.Figure 5.4(d) Actel ACT 2 and ACT 3 Logic Modules: T
2、he equivalent circuit (without buffering) of the SE (sequential element)Solution:a）由图中逻辑关系可以得出Q=(C1/C2+CLR)(/(C1C2) (/S1D+F1S1) MCF1+(C1C2)Q)(CLR+C1/C2)b)由于在设计中C1和C2至少要有一个接CLK(否则设计无意义)则编写相应的Hspice仿真代码如下* homeworkfive.sp- ACTEL ACT. D:Program Files (x86)synopsysHspice_D-2010.03-SP1MM018.L TT * Set TS
3、MC 0.18um library.option list node post.tran 50p 5000p* Starts a transient analysis that simulates a circuit at a specific time.* format: .TRAN tstep1 tstop1 .probe tran+ clock=par(v(C1)+ data=par(v(d)+ q=par(v(q)* Use this command to save output variables to interface and graph data* files. The par
4、ameter can be a node voltage or a reasonable expression.ic v(q)=0 $ set initial value. * The node voltages that you specify in the .IC statement are fixed to* determine the DC operating point. They are used only in the first * iteration to set an initial guess for the DC operating point analysis.* w
5、aveformsvdata d gnd pwl(0 0 100p 0 140p 1.8p 800p 1.8 840p 0 3.3n 0 3.34n 1.8)* pulse( v1 v2 td tr tf pw per )vclk c1 gnd pulse(0,1.8 300p,40p,40p 800p,1600p)vclr clr gnd pwl(0 1.8 4.2n 1.8 4.24n 0)vc1 c2 gnd 0* top: d-latch* xclkinv clck clckn inv $ enable if asymmetric (overlapping) positive* and
6、negative clocks are usedxact d c1 c2 clr q act cw1 qm gnd .1f $ add wire delaycw2 q gnd .1f* macro definitions* n-channel mosfet* drain gate source.subckt nmos n1 n2 n3mn n1 n2 n3 gnd NCH l=0.2u w=0.4u ad=0.2p2 pd=0.4u as=0.2p2 ps=0.4u .ends nmos* p-channel mosfet* drain gate source .subckt pmos n1
7、n2 n3vcc vcc gnd 1.8 *Vcc definitionmp n1 n2 n3 vcc PCH l=0.2u w=0.8u ad=0.4p2 pd=0.8u as=0.4p2 ps=0.8u.ends pmos*.subckt tgate in out c cnxmn in c out nmos *1 signal via nmosxmp in cn out pmos *0 signal via pmos.ends tgate*.subckt inv in outvcc vcc gnd 1.8xmn out in gnd nmosxmp out in vcc pmos.ends
8、 inv*.subckt or a b yvcc vcc gnd 1.8xmp1 d1 a vcc pmosxmp2 yn b d1 pmosxmn1 yn a gnd nmosxmn2 yn b gnd nmosxinv yn y inv.ends or*.subckt and a b yvcc vcc gnd 1.8xmp1 yn a vcc pmos xmp2 yn b vcc pmosxmn1 yn a s1 nmosxmn2 s1 b gnd nmosxinv yn y inv.ends and*.subckt xnor a b yvcc vcc gnd 1.8xand a b y1
9、 andxor1 a b y2 orxinv y2 y2n invxor2 y1 y2n y or.ends xnor*.subckt mux a b s zxinv s sn invxtg1 a z s sn tgatextg2 b z sn s tgate.ends mux*.subckt act d c2 c1 clr qxinv1 c1 c1n invxinv2 c2 c2n invxg1 c2 c1n s1 andxg2 c2n c1 t andxg3 c2 c1 s2 xnorxg4 t clr mc orxg5 qm d s1 m muxxg6 m mc qm andxg7 q
10、qm s2 s muxxg8 s mc q and.ends act*.end 如代码所示，假设C1接CLK而C2接地时，此时ACT芯片被配置成一个D触发器它在下降沿将D信号送入触发器，并且具有下降沿清零的功能。 C2接CLK而C1接地时，此时ACT芯片被配置成一个D触发器它在上升沿将D信号送入触发器，并且具有下降沿清零的功能。代码更改如下 clock=par(v(C2)+ data=par(v(d)+ q=par(v(q)* Use this command to save output variables to interface and graph data* files. The pa
11、rameter can be a node voltage or a reasonable expression.ic v(q)=0 $ set initial value. * The node voltages that you specify in the .IC statement are fixed to* determine the DC operating point. They are used only in the first * iteration to set an initial guess for the DC operating point analysis.*
12、waveformsvdata d gnd pwl(0 0 100p 0 140p 1.8p 800p 1.8 840p 0 3.3n 0 3.34n 1.8)* pulse( v1 v2 td tr tf pw per )vclk c2 gnd pulse(0,1.8 300p,40p,40p 800p,1600p)vclr clr gnd pwl(0 1.8 4.2n 1.8 4.24n 0)vc1 c1 gnd 0 C2接1而C1接CLK时，此时ACT芯片被配置成一个D触发器它在上升沿将D信号送入触发器，并且具有异步清零的功能。代码更改如下 + clock=par(v(C1)+ data=
13、par(v(d)+ q=par(v(q)* Use this command to save output variables to interface and graph data* files. The parameter can be a node voltage or a reasonable expression.ic v(q)=0 $ set initial value. * The node voltages that you specify in the .IC statement are fixed to* determine the DC operating point.
14、They are used only in the first * iteration to set an initial guess for the DC operating point analysis.* waveformsvdata d gnd pwl(0 0 100p 0 140p 1.8p 800p 1.8 840p 0 3.3n 0 3.34n 1.8)* pulse( v1 v2 td tr tf pw per )vclk c1 gnd pulse(0,1.8 300p,40p,40p 800p,1600p)vclr clr gnd pwl(0 1.8 4.2n 1.8 4.24n 0)vc1 c2 gnd 1.8很明显在第一个D信号处出现了亚稳定状态，判决出现了失误。C2接CLK而C1接1，CLR接1时，此时ACT芯片被配置成一个在低电平作用下的透明锁存器。代码更改如下+ clock=par(v(C2)+
