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1、CHAPTER8FLIP FLOPSANDRELATEDEDVICES Astable 非稳态的 Hold time 保持时间 Asynchronous 异步 Bistable 双稳态 Clear 清零 Dflip flop D触发器 Edge triggeredflip flop 边沿触发器 Feed back 反馈 Hysteresis 迟滞 J Kflip flop J K触发器 Latch 锁存器 Master slaveflip flop 主从触发器 KEYTERMS AstableHavingnostablestate Anastablemultivibratoroscillate
2、sbetweentwoquasistablestates AsynchronousHavingnofixedtimerelationship BistableHavingtwostablestates Flip flopsandlatchesarebistablemultivibrators ClearAnasynchronousinputusedtoresetaflip flop maketheQoutput0 Dflip flopAtypeofbistablemultivibratorinwhichtheoutputassumesthestateoftheDinputonthetrigge
3、ringedgeofaclockpulse Edge triggeredflip flopAtypeofflip flopinwhichthedataareenteredandappearontheoutputonthesameclockedge FeedbackTheoutputvoltageoraportionofitthatisconnectedbacktotheinputofacircuit HoldtimeThetimeintervalrequiredforthecontrollevelstoremainontheinputstoaflip flopafterthetriggerin
4、gedgeoftheclockinordertoreliablyactivatethedevice LatchAbistabledigitalcircuitusedforstoringabit HystersisAcharacteristicofathreshold triggeredcircuit suchastheSchmitttrigger wherethedeviceturnsonandoffatdifferentinputlevels J Kflip flopAtypeofflip flopthatcanoperateintheSET RESET no change andtoggl
5、emodes Master slaveflip flopAtypeofflip flopinwhichtheinputdataareenteredintothedeviceontheleadingedgesofclockpulsesandapperattheoutputontrailingedges Master slaveflip flopshave forthemostpart beenreplacedbyedge triggeredtypes MonostableHavingonlyonestablestate Amonostablemultivibrator commonlycalle
6、daone shot producesasinglepulseinresponsetoatriggeringinput One shotAmonostablemultivibrator PresetAnasynchronousinputusedtosetaflip flop maketheQoutput1 RESETThestateofaflip floporlatchwhentheoutputis0 theactionofproducingaRESETstate SETThestateofaflip floporlatchwhentheoutputis1 theactionofproduci
7、ngaSETstate Set uptimeThetimeintervalrequiredforthecontrollevelstobeontheinputstoadigitalcircuit suchasaflip flop priortothetriggeringedgeofaclockpulse S Rflip flopASET RESETflip flop SynchronousHavingafixedtimerelationship ToggleTheactionofaflip flopwhenitchangesstateoneachclockpulse 8 1LATCHES The
8、latchisatypeoftemporarystoragedevicethathastwostablestates bistable andisnormallyplacedinacategoryseparatefromthatofflip flop 2 Latchesarebasicallysimilartoflip flopsbecausetheyarebistabledevicesthatcanresideineitheroftwostatesusingafeedbackarrangement inwhichtheoutputsareconnectedbacktotheoppositei
9、nputs Themaindifferencebetweenlatchesandflip flopisinthemethodusedforchangingtheirstate 3 TheS R SET RESET Latch R S Q Q Active HIGHinputS Rlatch NORS RLatch 4 Q Q S R 5V R R R R R R 5 S R Q Q b Active LOWinputS Rlatch NANDS RLatch 6 S R Q Q WhenQisHIGH QisLOW andwhenQisLOW QisHIGH 7 InputOutputs SR
10、QQComments 11NCNCNochange latchremainsinpresentstate 0110LatchSET 1001LatchRESET 0011Invalidcondition TABLE8 1Truthtableforanactive LOWinputS Rlatch 8 InputOutputs SRQQComments 00NCNCNochange latchremainsinpresentstate 0101LatchRESET 1010LatchSET 1100Invalidcondition TABLE8 1 Truthtableforanactive H
11、IGHinputS Rlatch S R Q Q Active HIGHinputS Rlatch S R Q Q b Active LOWinputS Rlatch S R 9 EXAMPLE8 1 S R Q 10 EXAMPLE8 1 RelatedProblemDeterminetheQoutputofanactive HIGHinputS Rlatchifthewaveformsinaboveareinvertedandappliedtotheinput S R Q AlthoughSremainsLOWforonlyaveryshorttimebeforetheswitchboun
12、ce thisissufficienttosetthelatch TheGatedS RLatch S R Q Q EN S R EN a Logicdiagram b Logicsymbol 12 ThelatchwillnotchangeuntilENisHIGH butaslongasitremainsHIGH theoutputiscontrolledbythestateoftheSandRinputs EXAMPLE8 2DeterminetheoutputwaveformiftheinputsshowninFig 8 9areappliedtoagatedS Rlatchthati
13、sinitiallyRESET S R Q EN 13 Fig 8 9 a b EXAMPLE8 2 RelatedProblemDeterminetheQoutputofagatedS RlatchiftheSandRinputsinFig 8 9 a areinverted S R Q EN 13 Fig 8 9 a b TheGatedDLatch D Q Q EN D EN a Logicdiagram b Logicsymbol 14 Q Q Qn 1 D S R EXAMPLE8 3DeterminetheQoutputwaveformiftheinputsshowninFig 8
14、 11 a areappliedtoagatedDlatch whichisinitiallyRESET D Q EN 15 Fig 8 11 a EXAMPLE8 3RelatedProblemDeterminetheQoutputofthegatedDlatch iftheDinputinFig 8 11 a isreverted D Q EN a InputOutputs DENQQComments 0101RESET 1110SET X0Q0Q0Nochange Truthtable 16 Qn 1 D 8 2EDGE TRIGGEREDFLIP FLOPS Flip flopsare
15、synchronousbistabledevices alsoknownasbistablemultivibrators Inthiscase thetermsynchronousmeansthattheoutputchangesstateonlyataspecifiedpointonatriggeringinputcalledtheclock CLK whichisdesignatedasacontrolinputC thatis changesintheoutputoccurinsynchronizationwiththeclock 17 Edge triggeredflip flop S
16、 R Q Q C D Q Q C J K Q Q C S R Q Q C D Q Q C J K Q Q C Top positiveedge triggered bottom negativeedge triggered 18 TheEdge TriggeredS RFlip Flop S R Q Q C InputsOutputs 00XQ0Q0Nochange SRCLKQQComments 0101RESET 1010SET 11 Invalid 19 Qn 1 S RQn SR 0condition EXAMPLE8 4 S R Q Q C 1 2 3 4 5 6 S R Q CLK 20 EXAMPLE8 4DetermineQfortheSandRinputsinFig 8 16 a iftheflip flopisanegativeedge triggereddevice 1 2 3 4 5 6 S R Q CLK Pulse transition detector Q Q S R CLK 0 1 HIGH 1 LOW 0 0 1 0 1 0 1 0 1 Thisgat
