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1、DRAMBasicKnowledgeSummary HulinCao DRAMBasicKnowledge DRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe OrderDRAMControllerBasicDRAMControllerFunction ArchitectureAddressMappinginDRAMController DRAMBasicKnowledge DRAMDeviceArchitectureD
2、RAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe OrderDRAMControllerBasicDRAMControllerFunction ArchitectureAddressMappinginDRAMController DRAMDeviceArchitecture TypicalDRAMDeviceArchitectureSimple 1T 1CDatalosseswhenreadorover time DRAMDeviceArchitecture Da
3、taWidthofDRAMDeviceAlsothedatawidthofeachbankEachDRAMdevicewillhaveseveralbanks Cont d DRAMDeviceArchitecture Bank Rank Channel Cont d DRAMDeviceArchitecture Bank Cont d DRAMDeviceArchitecture Rank Cont d DRAMDeviceArchitecture Channel Cont d DRAMDeviceArchitecture OverviewofBank Rank Channel Cont d
4、 DRAMDeviceArchitecture Example TransferaCacheBlock Cont d 0 xFFFF F 0 x00 0 x40 64Bcacheblock Physicalmemoryspace Channel0 DIMM0 Rank0 Mappedto DRAMDeviceArchitecture Example TransferaCacheBlock Cont d 0 xFFFF F 0 x00 0 x40 64Bcacheblock Physicalmemoryspace Rank0 Chip0 Chip1 Chip7 Data 8B Row0Col0
5、8B DRAMDeviceArchitecture Example TransferaCacheBlock Cont d 0 xFFFF F 0 x00 0 x40 64Bcacheblock Physicalmemoryspace Data 8B 8B 8B Rank0 Chip0 Chip1 Chip7 Row0Col1 DRAMDeviceArchitecture Example TransferaCacheBlock Cont d 0 xFFFF F 0 x00 0 x40 64Bcacheblock Physicalmemoryspace Data 8B 8B Rank0 Chip0
6、 Chip1 Chip7 Row0Col1 A64Bcacheblocktakes8I Ocyclestotransfer Duringtheprocess 8columnsarereadsequentially DRAMBasicKnowledge DRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe OrderDRAMControllerBasicDRAMControllerFunction ArchitectureA
7、ddressMappinginDRAMController DRAMAccessFlow DRAMAccessFlowOverview DRAMAccessFlow DifferentialSenseAmplifier RowBuffer Cont d DRAMAccessFlow CircuitsofDifferentialSenseAmplifier Cont d DRAMAccessFlow ReadAccessStep1 WordLineSelect Cont d DRAMAccessFlow ReadAccessStep2 SenseAmplifier Cont d DRAMAcce
8、ssFlow ReadAccessStep3 Restore Cont d DRAMAccessFlow ReadAccessStep4 Pre charge Cont d DRAMAccessFlow SenseAmplifierVoltageWaveform ReadFlow Cont d DRAMAccessFlow WriteAccessFlow Cont d DRAMBasicKnowledge DRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommands TimingParametersDRAMCommandSchedulePageCl
9、osePageOpenBankInterleaveCommandsRe OrderDRAMControllerBasicDRAMControllerFunction ArchitectureAddressMappinginDRAMController DRAMBasicCommands KeyTimingParameters DRAMBasicCommands RowAccessCommand Activation Cont d DRAMBasicCommands ColumnReadCommand Cont d DRAMBasicCommands ColumnWriteCommand Con
10、t d DRAMBasicCommands PrechargeCommand Cont d DRAMBasicCommands RefreshCommand Cont d DRAMBasicCommands MoreaboutDRAMRefreshThememorycontrollerneedstorefresheachrowperiodicallytorestorechargeReadandcloseeachroweveryNmsTypicalN 64msDownsideofDRAMRefreshPowerConsumePerformancedegradationRefreshratelim
11、itsDRAMcapacityscaling Cont d DRAMBasicCommands MoreaboutDRAMRefreshRefreshMethodBurstrefreshDistributedrefresh Cont d DRAMBasicCommands MoreaboutDRAMRefresh Cont d DRAMBasicCommands MoreaboutDRAMRefresh Cont d DRAMBasicCommands DRAMRefreshinLPDDRxTCSRTemperatureCompensatedSelfRefreshEmbeddedtempera
12、turesensor adjustrefreshperiodbasedontemperature AlsoAdoptedinDDR4 PASRPartialArraySelfRefreshOnlyusepartoftheDRAMtosavepower Cont d DRAMBasicCommands AReadCycle Cont d DRAMBasicCommands PowerConsumeinDRAMReadCycle Cont d DRAMBasicCommands PowerRelatedTimingParameters tRRDtRRD RowtoRowactivationDela
13、y differentbankWillaffectDRAMcommandscheduling Cont d DRAMBasicCommands PowerRelatedTimingParameters tFAWtFAW FourBankActivationWindowWillaffectDRAMcommandscheduling Cont d DRAMBasicCommands ThevalueoftRRDandtFAWisPageSizeRelatedExample 1GbitDDR2SDRAMdevicefromMicron Cont d DRAMBasicCommands TheTren
14、doftRRDandtFAW Cont d DRAMBasicCommands tRRDandtFAWinDDR4 Cont d DRAMBasicKnowledge DRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageHit MissPageOpen ClosePolicyBankInterleaveCommandsRe OrderDRAMControllerBasicDRAMControllerFunction ArchitectureAddressMappinginDRAMControll
15、er DRAMCommandSchedule Page RowBuffer Hit MissPageHitNextRead WriteAccessisinthesamebank samerowAccessFlow Read WriteCommand DataTransactionPageMissNextRead WriteAccessisinthesamebank differentrowAccessFlow Prechargetothecurrentrow Activenextrow Read WriteCommand DataTransaction Cont d DRAMCommandSc
16、hedule Page RowBuffer Hit MissDemo Cont d RowBuffer Row0 Column0 Rowdecoder Columnmux Rowaddress0 Columnaddress0 Data Row0 Empty Row0 Column1 Columnaddress1 Row0 Column85 Columnaddress85 Row1 Column0 HIT HIT Rowaddress1 Row1 Columnaddress0 CONFLICT Columns Rows AccessAddress DRAMCommandSchedule PageOpenKeeptherowopenafteranaccessNextaccessmightneedthesamerow rowhitNextaccessmightneedadifferentrow rowconflict wastedenergyPageCloseClosetherowafteranaccess ifnootherrequestsalreadyintherequestbuffer
