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1、UART串口无法正确输出字符使用.s文件进行初始化设置，程序代码如下：; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRsMode_USR EQU 0x10Mode_FIQ EQU 0x11Mode_IRQ EQU 0x12Mode_SVC EQU 0x13Mode_ABT EQU 0x17Mode_UND EQU 0x1BMode_SYS EQU 0x1FI_Bit EQU 0x80 ; when I bit is set, IRQ is disabledF_Bit EQU 0x40 ; when F
2、bit is set, FIQ is disabledUND_Stack_Size EQU 0x00000000SVC_Stack_Size EQU 0x00000080ABT_Stack_Size EQU 0x00000000FIQ_Stack_Size EQU 0x00000000IRQ_Stack_Size EQU 0x00000100USR_Stack_Size EQU 0x00000400ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_S
3、ize) AREA STACK, NOINIT, READWRITE, ALIGN=3Stack_Mem SPACE USR_Stack_Size_initial_sp SPACE ISR_Stack_SizeStack_TopHeap_Size EQU 0x00000000 AREA HEAP, NOINIT, READWRITE, ALIGN=3_heap_baseHeap_Mem SPACE Heap_Size_heap_limit; System Control Unit (SCU) definitionsSCU_BASE EQU 0x5C002000 ; SCU Base Addre
4、ss (non-buffered)SCU_CLKCNTR_OFS EQU 0x00 ; Clock Control register OffsetSCU_PLLCONF_OFS EQU 0x04 ; PLL Configuration register OffsetSCU_SYSSTAT_OFS EQU 0x08 ; System Status Register OffsetSCU_PCGR0_OFS EQU 0x14 ; Peripheral Clock Gating Register 0 OffsetSCU_PCGR1_OFS EQU 0x18 ; Peripheral Clock Gat
5、ing Register 1 OffsetSCU_PRR0_OFS EQU 0x1C ; Peripheral Reset Register 0 OffsetSCU_PRR1_OFS EQU 0x20 ; Peripheral Reset Register 1 OffsetSCU_SCR0_OFS EQU 0x34 ; System Configuration Register 0 OffsetSCU_PECGR0_OFS EQU 0x2CSCU_PECGR1_OFS EQU 0x30SCU_GPIOOUT0_OFS EQU 0x44SCU_GPIOOUT1_OFS EQU 0x48SCU_G
6、PIOOUT2_OFS EQU 0x4CSCU_GPIOOUT3_OFS EQU 0x50SCU_GPIOOUT4_OFS EQU 0x54SCU_GPIOOUT5_OFS EQU 0x58SCU_GPIOOUT6_OFS EQU 0x5CSCU_GPIOOUT7_OFS EQU 0x60SCU_GPIOIN0_OFS EQU 0x64SCU_GPIOIN1_OFS EQU 0x68SCU_GPIOIN2_OFS EQU 0x6CSCU_GPIOIN3_OFS EQU 0x70SCU_GPIOIN4_OFS EQU 0x74SCU_GPIOIN5_OFS EQU 0x78SCU_GPIOIN6
7、_OFS EQU 0x7CSCU_GPIOIN7_OFS EQU 0x80SCU_GPIOTYPE0_OFS EQU 0x84SCU_GPIOTYPE1_OFS EQU 0x88SCU_GPIOTYPE2_OFS EQU 0x8CSCU_GPIOTYPE3_OFS EQU 0x90SCU_GPIOTYPE4_OFS EQU 0x94SCU_GPIOTYPE5_OFS EQU 0x98SCU_GPIOTYPE6_OFS EQU 0x9CSCU_GPIOTYPE7_OFS EQU 0xA0SCU_GPIOTYPE8_OFS EQU 0xA4SCU_GPIOTYPE9_OFS EQU 0xA8SCU
8、_GPIOEMI_OFS EQU 0xACSCU_WKUPSEL_OFS EQU 0xB0SCU_GPIOANA_OFS EQU 0xBCGPIO3_BASE EQU 0x58009000GPIO_DIR_OFS EQU 0x400GPIO_SEL_OFS EQU 0x420UART0_BASE EQU 0x5C004000UART1_BASE EQU 0x5C005000UART_FR_OFS EQU 0x18UART_ILPR_OFS EQU 0x20 UART_IBRD_OFS EQU 0x24 UART_FBRD_OFS EQU 0x28 UART_LCR_OFS EQU 0x2C U
9、ART_CR_OFS EQU 0x30 UART_IFLS_OFS EQU 0x34 UART_IMSC_OFS EQU 0x38UART_ICR_OFS EQU 0x44 UART_DMACR_OFS EQU 0x48; ConstantsSYSSTAT_LOCK EQU 0x01 ; PLL Lock Status; Flash Memory Interface (FMI) definitions (Flash banks sizes and addresses)FMI_BASE EQU 0x54000000 ; FMI Base Address (non-buffered)FMI_BBS
10、R_OFS EQU 0x00 ; Boot Bank Size RegisterFMI_NBBSR_OFS EQU 0x04 ; Non-boot Bank Size RegisterFMI_BBADR_OFS EQU 0x0C ; Boot Bank Base Address RegisterFMI_NBBADR_OFS EQU 0x10 ; Non-boot Bank Base Address RegisterFMI_CR_OFS EQU 0x18 ; Control Register; APB Bridge 1 & 2 definitions (Peripherals)APB0_BUF_
11、BASE EQU 0x48001802 ; APB Bridge 0 Buffered Base AddressAPB0_NBUF_BASE EQU 0x58000000 ; APB Bridge 0 Non-buffered Base AddressAPB1_BUF_BASE EQU 0x4C000000 ; APB Bridge 1 Buffered Base AddressAPB1_NBUF_BASE EQU 0x5C000000 ; APB Bridge 1 Non-buffered Base AddressFMI_CR_Val EQU 0x00000018 ;0FMI_BBSR_Va
12、l EQU 0x00000004 ;1FMI_BBADR_Val EQU 0x00000000 ;2FMI_NBBSR_Val EQU 0x00000002 ;3FMI_NBBADR_Val EQU 0x00400000 ;4FLASH_CFG_Val EQU 0x00000000 ;5STARTUPEQU1;0SCU_CLKCNTR_Val EQU 0x00031404 ;1SCU_PLLCONF_Val EQU 0x000BC019 ;2SCU_SYSSTATUS_Val EQU 0x0000003F ;3SCU_PWRMNG_Val EQU 0x00000000 ;4SCU_ITCMSK_Val EQU 0x00000001 ;5SCU_PCGR0_Val EQU 0x000000FB ;6SCU_PCGR1_Val EQU 0x01FFCC39 ;7SCU_
