ds18B20 FPGA(VHDL语言)

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1、-VHDL语言编写DS18B20温度传感器程序library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ds18B20 is port(clk : in std_logic; -50MHz dq : inout std_logic; rst: in std_logic; LED : out std_logic; LED2 : out std_logic; LED3 : out std_logic; dataout1,dataou

2、t2,dataout3 : out std_logic_vector(6 downto 0 ); -数end ds18B20; architecture Behavioral of ds18B20 is TYPE STATE_TYPE is (RESET,CMD_CC,WRITE_BYTE,WRITE_LOW,WRITE_HIGH,READ_BIT, CMD_44,CMD_BE,WAIT800MS,GET_TMP,WAIT4MS); signal STATE: STATE_TYPE:=RESET; signal clk_temp : std_logic:=0; signal clk1m : s

3、td_logic; -分频后得到的1M时钟 signal cp: std_logic; - 1ms 时钟signal w : integer range 0 to 2 :=0; - xian shi shun xu signal write_temp : std_logic_vector(7 downto 0):=00000000; signal TMP : std_logic_vector(11 downto 0); signal tmp_bit : std_logic; signal WRITE_BYTE_CNT : integer range 0 to 8:=0; signal WRIT

4、E_LOW_CNT : integer range 0 to 2:=0; signal WRITE_HIGH_CNT : integer range 0 to 2:=0; signal READ_BIT_CNT : integer range 0 to 3:=0; signal GET_TMP_CNT : integer range 0 to 13:=0; signal cnt : integer range 0 to 100_001:=0; -* signal cnt2 : integer range 0 to 4000001:=0; signal temp : std_logic; sig

5、nal data_temp0 : std_logic_vector(15 downto 0); signal decimal0 : std_logic_vector(15 downto 0); signal decimal1 : std_logic_vector(15 downto 0); signal decimal2 : std_logic_vector(15 downto 0); signal decimal3 : std_logic_vector(15 downto 0); signal data_temp1 : std_logic_vector(7 downto 0); signal

6、 integer0 : std_logic_vector(7 downto 0); signal integer1 : std_logic_vector(7 downto 0); signal integer2 : std_logic_vector(7 downto 0); signal integer3 : std_logic_vector(7 downto 0); signal integer4 : std_logic_vector(7 downto 0); signal integer5 : std_logic_vector(7 downto 0); signal integer6 :

7、std_logic_vector(7 downto 0); signal sign : std_logic_vector(7 downto 0); signal count : integer range 0 to 51:=0; signal WRITE_BYTE_FLAG : integer range 0 to 4:=0; function dis(num: std_logic_vector) return std_logic_vector isbegin case num is when 0000 = return 1000000; -0 when 0001 = return 11110

8、01; -1 when 0010 = return 0100100; -2 when 0011 = return 0110000; -3 when 0100 = return 0011001; -4 when 0101 = return 0010010; -5 when 0110 = return 0000010; -6 when 0111 = return 1111000; -7 when 1000 = return 0000000; -8 when 1001 = return 0010000; -9 when 1010 = return 0001000; -A when 1011 = re

9、turn 0000011; -b when 1100 = return 1000110; -C when 1101 = return 0100001; -d when 1110 = return 0000110; -E when 1111 = return 0001110; -F when others = return 1111111; -mie end case; end dis; begin -ClkDivider:process (clk,clk_temp) begin if rising_edge(clk) then if (count = 24) then count = 0; c

10、lk_temp= not clk_temp; else count = count +1; end if; end if; clk1m12000) then n:=0; cp=not cp; end if; end if; end Process; STATE_TRANSITION:process(STATE,clk1m) begin if rising_edge(clk1m) then if(rst=0) then STATE -* LED2=0;-*- LED3=0 and cnt500) then - 500s的复位低电平 dq=0;- dq作为输出 cnt=cnt+1; STATE=5

11、00 and cnt510) then -高阻态再输入下一级电路的话,对下级电路无任何影响,和没接一样,高阻态可以应用在inout端口里面,这样在inout没有输出的时候就弄个高阻态,这样就其电平就可以由外面的输入信号决定了dq=Z; cnt=cnt+1; STATE=510 and cnt750) then - 240stemp=dq; - dq作为输入if(cnt=580) then temp=dq; if(temp=1) then LED=0; else LED=1; end if; end if; cnt=cnt+1; STATE=750) then cnt=0; -计数器清零 STA

12、TE -跳跃rom指令“CC”LED2=1; LED3=0; write_temp=11001100; STATE case WRITE_BYTE_CNT is when 0 to 7= if (write_temp(WRITE_BYTE_CNT)=0) then STATE=WRITE_LOW; LED3=1; else STATE=WRITE_HIGH; end if; WRITE_BYTE_CNT if (WRITE_BYTE_FLAG=0) then - 第一次写0XCC完毕 STATE=CMD_44; WRITE_BYTE_FLAG=1; elsif (WRITE_BYTE_FLAG=1) then -写0X44完毕 (写温度转换指令后没有读数据?) STATE=RESET

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