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1、1/103Low-k Wire Bonding2/103low-klow-k低介電值低介電值所謂low-k (低介電值）就是尋找介電常數較小的材料，以降低導線間電流的互相干擾作用，進而提升IC內導線傳輸功能。低介電係數絕緣體的界電係數通常被定義為值低於3。由於電路信號傳遞的快慢是決定在電阻(R)與電容(C)乘積，RC乘積值越小，速度就越快。因此，降低電容值亦可改善傳輸速度。而電容值則與IC上金屬線間絕緣介電材料的介電係數K相關，K越小，電容值越小。電容的大小，會跟平行板中的所放的介電物質有關： 其中 為電容率（permittivity）C= k E A/ d （A為平行板面積，d為平行板間距）
2、 根據1837年法拉第發現，物質的介電係數與其電容有關，他定義了介電常數。一直作為金屬導線間絕緣材料的化二氧化矽(SiO2)，介電係數約為3.94.5間，然當製程不斷推進，二氧化矽己逐漸接近應用上的極限。一般用於金屬導線間的介電材質層(Intermetal dielectric)，簡稱為IMD，其規格要求為高可靠度、低應力、製程簡單化、不易吸水和易於與金屬導線間作整合。FSG (氟矽玻璃)係以二氧化矽材料為基礎，再加入氟，以降低電介薄膜的電容值(k)。名詞解釋3/103銅製程到底跟一般製程有什麼地方不一樣銅製程到底跟一般製程有什麼地方不一樣? ? 隨著線寬的縮小，元件運算的速度便會受到電阻質的
3、增加而顯著的下降特別是0.25微米世代以下。為了面對更密集的電路設計，金屬材料如銅為一具有更低電阻材質的來取代鋁。為了降低訊號傳遞的時間延遲，具有低電阻和低電容的材料，便因此應蘊而生。在低電阻部份，金屬銅由於具有高熔點，低電阻係數(1.7mW-cm) ，因而成為最有希望取代金屬鋁的金屬材質。另一方面，在低電容部份，電容C=e (A/d)，由於製程上及導線電阻的限制，使我們不考慮藉由幾何上的改變（例如：改變導線面積）來降低寄生的電容值。因此，具有低介電常數(low k)材質（可分為無機類及有機類聚合物）的研究，就成為主要的發展趨勢。名詞解釋4/103Cu / low-k is the well-
4、known solution to reduce signal delay and improve electrical performance for advanced IC. But the mechanical properties of Cu /low-k are poorer than Al/Si oxide combination.This study investigates the impact of packaging process and molding compound to achieve successful integration of Cu/low-k with
5、 assembly. IntroductionCuCuLow K Low-kCopper Low-kCopper Barrier Barrier5/103Failure Mode Effect AnalysisLow-k dielectrics with poor characteristics result in novel challenges to assembly process.Process Possible Failure ModeSolutionDie SawWire BondMoldingPassivation peelInterlayer delaminationRobus
6、t cut street structureOptimum saw parametersPoor bond strengthDamage to the bond padOptimum wire bond parametersRobust bond pad structureInterlayer delaminationLow stress mold compound6/103Part I - Assembly Process Investigation (1) ( Die Saw Process )The purpose of this study is to confirm if the c
7、onventional saw process could still be applied to low-k wafer.Group 1 :Group 2 :Basic Information :Low-k wafer : B companyLow-k dielectric : C typeTotal / low-k layer : 7 / 1Line width : 90nmLaser + Blade CutBlade CutFeed Rate : 150 mm/sPower : 2WRep. Rate : 100k HZBlade TypeFeed rateRPMZ1Z250 mm/s5
8、0 mm/s40k40kExperimental Design :Z1Z2SiliconLow KZ1Z2SiliconLow K7/103名詞解釋關於關於laser cutlaser grooving + blade dicing2nd stepSi1st stepSi Street width Low-K layer8/103Normal cutLaser+normal cutPeeling in pads9/103Result & Discussion (1)Group 1 : Die saw by laser, no delamination was found after TCT 1
9、000 with low stress EMC.Group 2 : Although peeling was found by conventional blade saw, no interlayer delamination after TCT 1000 with low stress EMC. 10/103Conventional blade saw process cant prevent passivation peeling for low-k device. But the chips seal ring will stop the peeling. The blade saw
10、process can be applied to low-k wafer if with low stress EMC. Seal ring stop the passivation peelingAfter TCT 1000After die sawConclusion11/103關於關於 molding compound vs. low k deviceEvaluation of Molding CompoundThe results showed that low CTE and low stress molding compounds are more suitable for lo
11、w k chip package. (Coefficient thermal expansion) Six molding compounds were selected for the low k package evaluation and their properties are listed in table 2. After the package assembly, the test samples were subjected to precondition MSL3a test followed by TCT.名詞解釋12/103Part I - Assembly Proces
12、s Investigation (2) ( Wire Bond Process )The purpose is to study any damage to bond pad for low-k structure with wire bonding process.Test Vehicle: Optimized process windowBond time: 15msUSG current: 5062mA Bond force: 1115mA Gold wire : S xx 0.9milsCapillary : M xxWire Bonder: K xxPad pitch: 60um P
13、ad open: 52*61umDie size: 8.0 * 8.0mmPackage: BGA 37.5 * 37.5 552 I/O1st bond graphical optimization:Variable factors:Bond temperature: 16013/103CIC : (Contained Inner Chamfer) The CIC capillary contains most of the additional gold generated from first bond formation in its inner chamfer. Consistent
14、, repeatable intermetallic coverage reduces pad peeling, cratering and non-stick occurrences.名詞解釋14/103The capillaries produced with the ATLAS material possess the following features: Higher fracture toughness supporting extremely small wall thickness Tighter tool tolerances increasing the process s
15、tability and robustness Smaller grain size enabling smoother surface finish and smaller hole diameter名詞解釋15/103Wire Bond Result (2)Bonded ball size :The bonded ball diameter meet the target, and the shape shows acceptable.Cross-section image : The cross-section images show no ball bonding related da
16、mage on pad structure.16/103Wire Bond Result (2)IMC image : The IMC coverage at 0hr, all are uniform.Cratering test : The bond pads after etching. No oxide layer crack were observed. All the quality check items, the performance are similar with Al/Si oxide wafer. 17/103Mold condition : Part I - Asse
17、mbly Process Investigation (3) ( Molding Process )Mold Temp: 175 C / 175 C Transfer Pressure: 75 kg / cm2Transfer time: 13.9 secClamp force: 20 tons Cure time: 120 sec No Inner Delamination after MoldingchipSubstrateEpoxyEMC18/103Part II - Material Evaluation (EMC)In order to verify the effect of mo
18、lding compound on WB-PBGA stress, there are two stages studies to investigate the stress distribution over die. ( Stage 1 3D Model )Stag-1 Model :- a quarter 3D model- die size 8mmx8mm and 16mmx16mm- thermal loading conditions are 150 to -65 Die size: 8mmx8mmDie size: 16mmx16mm19/103Die shear stress
19、: 4.44kg/mm2Die shear stress: 2.51kg/mm2Die shear stress: 4.71kg/mm2Die shear stress: 2.70kg/mm2Die size: 8mmx8mmM/C: normalDie size: 16mmx16mmM/C: normalDie size: 8mmx8mmM/C: low stressDie size: 16mmx16mmM/C: low stressDie centralDie centralDie centralDie central1. Max. die shear stress is located
20、at die corner. (Please see attached plots)2. Low-stress molding compound has lower die corner shear stress.Simulation Result ( Stage 1 3D Model )20/103Stag-2 Model :- a half 2D model- die size 8mmx8mm and 16mmx16mm- thermal loading condition is 150 to -65 - low-k structure is added above the die top
21、.Die size: 8mmx8mmDie size: 16mmx16mmSilicon Die,Metal-1 (Cu)Low-kMetal-2 (Cu)Metal-3 (Cu)Metal-4 (Cu)Metal-5 (Cu)Metal-6 (Cu)Pad metal-7 (Al)FSGLow-kLow-kLow-kLow-kLow-kLow-k structure ( Stage 2 2D Model )21/1031. Max. die shear stress is also located at bottom layers between low-k and metal layers
22、 near silicon die. 2. Low-stress molding compound has lower die corner shear stress.Max. shear stress: 7.94kg/mm2Max. shear stress: 10.06kg/mm2Max. shear stress: 7.94kg/mm2Die size: 8mmx8mmM/C: normalDie size: 16mmx16mmM/C: normalDie size: 8mmx8mmM/C: low stressDie size: 16mmx16mmM/C: low stressMax.
23、 shear stress: 10.06kg/mm2Simulation Result ( Stage 2 2D Model )22/1031. Low stress molding compound effectively reduces the die corner shear stress for both the die size of 8mmx8mm and 16mmx16mm to prevent the low-k layer peeling. 2. In stage 2 study, the max. shear stress is located at the edge of
24、 low-k bottom layer and silicon die. There is consistency between failure mode and simulation result.DieCompoundThrough scan found delamination at the corner of the die. C-Scan showed that delamination is in the die. X-section found metal peeling. DieCompoundMax. shear stress at the edge of low-k bo
25、ttom layer and silicon die.Simulation Result23/103Part III Wafer Fabrication (Cut Street Structure)By TCT and SAT inspection, structure 2 & 3 have lower defect rate of delamination. The structure 2 & 3 effectively hold the metal layer and fixed SiO2, thus indicated the mechanical strength are robust
26、 compared to the conventional structure.The scribe line structure pattern will play an important role to prevent interlayer delamination. Three kind of patterns are evaluated in this study.24/103Summary1.In this study, the influence of each assembly process on Cu/low-k is investigated, and the delam
27、ination isnt clearly matched with the specific stress generated in the assembly process.2.Through FEA modeling, it is determined that interlayer delamination of Cu/low-k may be minimized if the EMC material has a lower stress.3.Three cut street structure are evaluated, and the array / stagger filler stack are more robust than conventional type.
