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1、International Center on Design for Nanotechnologies(IC-DFN)http:/ Center on Design for Nanotechnologies(IC-DFN)International Center on Design for Nanotechnologies(IC-DFN)Project SummaryEstablish an International Center on Design for Nanotechnologies (IC-DFN)Project focusDesign methodologies Systems-
2、level issuesInternational collaboration to leverage global investment and coordinate researchhttp:/ Center on Design for Nanotechnologies(IC-DFN)International Center on Design for Nanotechnologies(IC-DFN)Current Research TeamUSUCLA: Jason Cong (Center co-director) and Kang WangUC Santa Barbara: Tim
3、Cheng (Center co-director) and Evelyn HuTaiwanNational Tsinghua University (NTHU): Shih-Chieh Chang (Taiwan coordinator) Cheng Chung Chi, Shi-Yu Huang, Tingting Hwang, Youn-Long Lin, C. L. Liu, Cheng-Wen WuNational Taiwan University (NTU): Yao-Wen Chang, Juin-Lang Huang, Chien-Mo Li, Ric HuangChinaT
4、singhua University (THU): Jinian Bian, Xianlong Hong (China coordinator)Peking University (PKU): Xu Cheng, Ru HuangZhejiang University (ZJU): Xiaolang Yan, Zhizhen Yehttp:/ Center on Design for Nanotechnologies(IC-DFN)International Center on Design for Nanotechnologies(IC-DFN)Division of Research an
5、d Educational Taskshttp:/ Center on Design for Nanotechnologies(IC-DFN)International Center on Design for Nanotechnologies(IC-DFN)Research OverviewThrust 1: Technology and Architecture/Platform DriverTechnology DriverArchitecture/Platform Driver:nano-FPGAThrust 2: Design for Nano-TechnologyDesign fo
6、r RobustnessEnable Higher Level of AbstractionEfficient Solutions to Fundamental Design Automation ProblemsThrust 3: Design/Application DriverMulti-Core Heterogeneous SOC Design in Nanotechnologieshttp:/ Center on Design for Nanotechnologies(IC-DFN)International Center on Design for Nanotechnologies
7、(IC-DFN)Thrust 1(a): Technology Driver (Led by Kang Wang and Evelyn Hu)Technology characterization, in terms of reliability, process variation, etc. (UCSB, ZJU)Design of circuit blocks, e.g. memory cells, logic gates, and multiplexors (UCLA, PKU)Bottom-up assembly techniques (UCSB, NTHU)http:/ Cente
8、r on Design for Nanotechnologies(IC-DFN)International Center on Design for Nanotechnologies(IC-DFN)Thrust 1(b) Architecture/Platform Driver:nano-FPGA (Led by Jason Cong and Kang Wang)Technology characterization, in terms of reliability, process variation, etc. (UCLA, UCSB, ZJU)Exploration of reconfi
9、guration technologies (PKU and UCLA)Circuit-level design of nano-FPGA (PKU and UCLA)Logic-level design of nano-FPGA (UCLA and NTHU)Basic design flow for mapping gate-level circuits to nano-FPGAs (UCLA, NTU and THU)http:/ Center on Design for Nanotechnologies(IC-DFN)International Center on Design for
10、 Nanotechnologies(IC-DFN)Thrust 2(a) Design for Robustness (Led by Tim Cheng)Exploring tradeoffs between reconfiguration and redundancy for reliable design (UCSB)On-line/off-line self-test and self-diagnosis to support reconfiguration (UCSB)Architectural design for timing-error-tolerance (NTHU, NTU,
11、 and UCSB)Functional error tolerance for nano-FPGA and nano-structured ASIC (NTHU) CAD issues on synthesis, mapping, and routing of reliable design with built-in reconfiguration and redundancy capabilities (NTHU, NTU, and ZJU) http:/ Center on Design for Nanotechnologies(IC-DFN)International Center
12、on Design for Nanotechnologies(IC-DFN)Thrust 2(b) Enable Higher Level of Abstraction(Led by Jason Cong)System-level performance modeling and estimation (UCLA)System-level and behavior-level synthesis (UCLA and THU)System-level and behavior-level property check and equivalence checking (UCSB)http:/ C
13、enter on Design for Nanotechnologies(IC-DFN)International Center on Design for Nanotechnologies(IC-DFN)Thrust 2(c): Efficient Solutions to Fundamental Design Automation ProblemsEfficient high-level satisfiability checking (UCSB)Multilevel optimization (UCLA and NTU)Efficient solver for large-scale l
14、inear systems (THU and NTHU)Multi-space search and search space smoothing (THU)http:/ Center on Design for Nanotechnologies(IC-DFN)International Center on Design for Nanotechnologies(IC-DFN)Thrust 3 Design Driver(Led by Prof. Youn-Long Lin)Multi-Core Heterogeneous SOC Design in Nanotechnologies CPU
15、core designs (PKU), DSP core designs (ZJU), and video codec designs (NTHU)On-chip interconnect structure design (NTHU)http:/ Center on Design for Nanotechnologies(IC-DFN)International Center on Design for Nanotechnologies(IC-DFN)Education(Led by Prof. Cheng, Prof. Hu and Prof. Cong)Semi-annual works
16、hops (locations rotating among the U.S., mainland China and Taiwan)Web seminarsEstablishment of international internshipsPartnership with UC EAP program, joint activities with IPAM (UCLA) and CMS (ZJU)Providing seminars to WiSE and/or MESA and participate in CNSIs INSET and EPSEM programshttp:/ Cent
17、er on Design for Nanotechnologies(IC-DFN)International Center on Design for Nanotechnologies(IC-DFN)Focus of Years 1 & 2 (US Team)Thrust 1: Technology and Architecture/Platform DriverTechnology DriverArchitecture/Platform Driver:nano-FPGAThrust 2: Design for Nano-TechnologyDesign for RobustnessEnabl
18、e Higher Level of AbstractionEfficient Solutions to Fundamental Design Automation ProblemsThrust 3: Design/Application DriverMulti-Core Heterogeneous SOC Design in Nanotechnologieshttp:/ Center on Design for Nanotechnologies(IC-DFN)International Center on Design for Nanotechnologies(IC-DFN)Internati
19、onal Collaboration ActivitiesProposal planning meetings on Nov. 2004 (Hawaii) and Jan. 2005 (Shanghai)Proposal submitted to NSF in March 2005 and funded in October 20051st IC-DFN workshop in Jan. 2006, Huilian, Taiwan2nd IC-DFN workshop in Aug. 2006, Hangzhou, Chinahttp:/ Center on Design for Nanotechnologies(IC-DFN)International Center on Design for Nanotechnologies(IC-DFN)
