《计算机组成教学课件：Chapter2-Instructions&InstructionSequencing》由会员分享，可在线阅读，更多相关《计算机组成教学课件：Chapter2-Instructions&InstructionSequencing（105页珍藏版）》请在金锄头文库上搜索。
1、Computer Organization & Architecture Chapter 2 Instructions Set ArchitectureContent of this lecturen2.3 Instruction and Instruction SequencingnInstruction Formatsn2.4 Addressing Modesn2.6 Stacksn2.7 Subroutinesn2.8 Additional Instructionsn2.10 CISC Instruction Setsn2.11 RISC and CISC Stylesn2.3 Inst
2、ruction and Instruction SequencingRegister Transfer NotationAssembly-Language NotationRISC and CISC Instruction SetsIntroduction to RISC Instruction SetsInstruction Execution and Straight-Line SequencingBranchingInstruction and Instruction Sequencing (1)nFour Types of InstructionsData transfers betw
3、een the memory and the processor registersArithmetic and logic operations on dataProgram sequencing and controlI/O transfersnRegister Transfer NotationMemory Location: LOC, PLACE, A, VAR2Processor Register: R0, R5I/O Subsystem Register: DATAIN, OUTSTATUSThe contents of any location are denoted by pl
4、acing square brackets around its name: R2 LOCRegister Transfer Notation: R4 R2 + R3nThe righthand side of an RTN expression always denotes a value, and the left-hand side is the name of a location where the value is to be placed, overwriting the old contents of that location.Instruction and Instruct
5、ion Sequencing (2)nAssembly-Language NotationExample1: Load R2, LOCnThe transfer from memory location LOC to processor register R2Example2: Add R4, R2,R3nRegisters R2 and R3 hold the source operands, while R4 is the destination.nMnemonicsAssembly languages for different processors often use differen
6、t mnemonics for a given operation.E.g. Load LD Store STR or STInstruction and Instruction Sequencing (3)nRISC and CISC Instruction SetsDesign a computer starting by defining ISA.What is instruction set architecture (ISA)?ISAnDefines registersnDefines data transfer modes (instructions) between regist
7、ers, memory and I/OnThere should be sufficient instructions to efficiently translate any program for machine processingNext, define instruction set format binary representation used by the hardwarenVariable-length vs. fixed-length instructionsInstruction and Instruction Sequencing (4)nRISC and CISC
8、Instruction Sets (ctd.)Types of ISAnReduced instruction set computer (RISC)Small set of instructions (typically 32)Simple instructions, each executes in one clock cycle REALLY? Well, almost.Effective use of pipeliningExample: ARMnComplex instruction set computer (CISC)Many instructions (several hund
9、reds)An instruction takes many cycles to executeExample: Intel PentiumInstruction and Instruction Sequencing (5)nIntroduction to RISC Instruction Sets Two key characteristics of RISC instruction setsnEach instruction fits in a single word.nA load/store architecture is used, in whichMemory operands a
10、re accessed only using Load and Store instructions.All operands involved in an arithmetic or logic operation must either be in processor registers, or one of the operands may be given explicitly within the instruction word.Instruction and Instruction Sequencing (6)nIntroduction to RISC Instruction S
11、ets (ctd.)Load Instruction FormatnLoad destination, sourcenLoad processor_register, memory_locationStore Instruction FormatnStore source, destinationAdd Instruction FormatnAdd destination, source1, source2Instruction and Instruction Sequencing (7)nIntroduction to RISC Instruction Sets (ctd.) Example
12、: C = A + B C A + BnLoad R2, AnLoad R3, BnAdd R4, R2, R3nStore R4, CInstruction and Instruction Sequencing (8)nInstruction Execution and Straight-Line SequencingExample: C = A + BC A + BAssume thatnThe word length is 32 bitsnThe memory is byte-addressablenA desired memory address can be directly spe
13、cified in Load and Store instructions.Instruction and Instruction Sequencing (9)nInstruction Execution and Straight-Line Sequencing (ctd.)Straight-line SequencingPC= iPC= i +4Instruction FetchInstruction ExecuteInstruction and Instruction Sequencing (10)nBranchingAdding a list of n numbersnSeparate
14、Load and AddInstructionsInstruction and Instruction Sequencing (11)nBranching (ctd.)Adding a list of n numbersnA program loopnBranch InstructionsLoad a new address into the PCBranch TargetnConditional BranchCompare the contents of tworegistersBranch_if_R4R5 LoopCondition Codesn补充内容：Instruction Forma
15、tsElements of A Machine InstructionInstruction Address Field FormatOpcode FormatExample of Instruction FormatInstruction Formats (1)nWhat is Machine Instruction?The instructions which specify the actions that must be performed by the processor circuitry to carry out the desired tasks.Machine CodeBin
16、aryUsually represented by assembly codes.nWhat is Instruction Set?The collection of different machine instructions that the processor can execute.Instruction Format (2)nElements of A Machine InstructionOperation codenSpecify the operation to be performed (e.g.,ADD, I/O), expressed as a binary code.S
17、ource operand referencenOperands required for the instruction are specified.Result operand referencenWhere should the result of the operation be placed?nSource and result operands can be in one of three areas:Main or virtual memory or cacheProcessor registerI/O deviceInstruction Format (3)nElements
18、of A Machine Instruction (ctd.)Next instruction reference nHow / where is the next instruction to be found.In most cases, this is not explicitly stated in the instruction.Next instruction is the one that logically follows the current one in the program (sequential / linear progression through the pr
19、ogram).nInstruction RepresentationWithin the computer, each instruction is represented by a sequence of binary bits. Instruction Formats (4)nInstruction Representation (ctd.)The instruction is divided into fields:nOperation code field: Specify the operation to be performed.nAddress fieldnInstruction
20、 Design CriteriaShort instructions are better than long ones.Sufficient room in the instruction format to express all the operations desired.Number of bits in the address field.Instruction Formats (5)nInstruction Address Field Format Zero-address InstructionOne-address InstructionnOP A AnAC OP A ACT
21、ypically, it is understood implicitly that a second operand is in the accumulator of the processorInstruction Format (6) nInstruction Address Field Format (ctd.)Two-address InstructionnA1 OP A2 A1nA1: Destination operand addressnA2: Source operand addressThree-address FormatnA1 OP A2 A3Instruction F
22、ormat (7)nInstruction LengthFixed length: All instructions have the same lengthVariable Length: Instructions may be many different lengthsInstruction Format (8)nInstruction Length (ctd.) Methods to Reduce Instruction LengthnIf the operand is to be used several times, it can be moved into a register.
23、 (If an operand is to be used only once, putting it in a register is not worth it.)nSpecify one or more operands implicitly.Instruction Format (9)nOpcode FormatFixed-length OpcodenInstruction length: n + k bits nk bits opcode and n bits operand addressAllows for 2k different operationsAllows for 2n
24、addressable memory cellsnk-1 bit opcode and n+1 bit addressHalf as many instructions but twice the addressable memorynk+1 bit opcode and n-1 bit addressTwice as many instructions but half the addressable memoryInstruction Format (10)nOpcode Format (ctd.)Variable-length Opcode (Expanding Opcode)nExam
25、ple: Instruction length is 16-bit, operand address is 4-bit.This might be reasonable on a machine that has 16 registers on which all arithmetic operations take place.One design would be a 4-bit opcode and three addresses in each instruction, giving 16 three-address instructions.Instruction Format (1
26、1)nOpcode Format (ctd.)Variable-length Opcode (Expanding Opcode) (ctd.)nExample: Instruction length is 16-bit, operand address is 4-bit. (ctd.)Suppose the designers need:15 three-address instructions14 two-address instructions31 one-address instructions16 zero-address instructionsHow should we desig
27、n the instruction format?Instruction Format (12)nOpcode Format (ctd.)Variable-length Opcode (Expanding Opcode) nExample: (ctd.)Three-address instruction4-bit opcode 0000 1110 (15 12 bit)Instruction Format (13)nOpcode Format (ctd.)Variable-length Opcode (Expanding Opcode) nExample: (ctd.)Two-address
28、instruction8-bit opcode 11110000 11111101 (15 8 bit)1111 (15 12 bit) 0000 1101 (11 8 bit)Instruction Format (14)nOpcode Format (ctd.)Variable-length Opcode (Expanding Opcode) nExample: (ctd.)One-address instruction12-bit opcode 111111100000 111111111110 (15 4 bit)Instruction Format (15)nOpcode Forma
29、t (ctd.)Variable-length Opcode (Expanding Opcode) nExample: (ctd.)Zero-address instruction16-bit opcode 1111111111110000 - 1111111111111111Instruction Format (16)nOpcode Format (ctd.)Variable-length Opcode (Expanding Opcode) nSummaryExpanding Opcodes demonstrates a trade-off between space for Opcode
30、 and space for other information.Carrying variable Opcode to an extreme, it is possible to minimize the average instruction length by encoding every instruction to minimize bits needed.However, this will result in instructions of various sizes that are not even aligned on byte boundaries.Expanding O
31、pcodes is typically employed at the byte level like the above example. Instruction Format (17)nExample of Instruction FormatInstruction Format (18)nExample of Instruction Format (ctd.)n2.4 Addressing ModesImmediate ModeAbsolute ModeRegister ModeRegister Indirect ModeIndirect ModeIndex ModeAddressing
32、 Modes (1)nHow to specify where an operand for an instruction is located?nHow the bits of an address field in an instruction are interpreted?nWhat is Addressing Modes?The different ways in which the location of an operand is specified in an instruction are referred to as addressing modes.Addressing
33、Modes (2)nTypical Addressing ModesAddressing Modes (3)nImmediate ModeThe operand is given explicitly in the instruction.Example: Add R4, R6, #200UsagenDefine and use constants nSet initial values of variablesAdvantagenNo memory reference other than the instruction fetch is required to obtain the ope
34、rand.DisadvantagenOnly a constant can be supplied this way.nThe size of the number is limited by the size of the address field.OPOperandAddressing Modes (4)nAbsolute Mode The operand is in a memory location; the address of this location is given explicitly in the instruction.Example: Integer NUM1, N
35、UM2, NUM3 Load R2 NUM1EA = AEA : actual (effective) address of the location containing the referenced operandA: contents of an address field in the instructionIn a system without virtual memory, the effective address will be either a main memory address or a register.Addressing Modes (5)nAbsolute Mo
36、de (ctd.)In a virtual memory system, the effective address is a virtual address or a register addressUsagenAccess global variables whose address is known at compile time. AdvantagenOnly one memory reference and no special calculation.DisadvantagesnThe instruction will always access exactly the same
37、memory location.nIt provides only a limited address space.Addressing Modes (6)nRegister Mode The operand is the contents of a processor register; the address of the register is given in the instruction.EA = RiRi : contents of an address field in the instruction that refers to a register.Example Add
38、R4, R2, R3UsagenAccess variables which are accessed most oftenAddressing Modes (7)nRegister Mode (ctd.)AdvantagesnOnly a mall address field is needed in an instruction.nNo memory reference references are required.DisadvantagenThe address space is very limitedAddressing Modes (8)nRegister Indirect Mo
39、de The effective address of the operand is the contents of a register that is specified in the instruction.EA = RiAddressing Modes (9)nRegister Indirect Mode (ctd.)Example Load R2, (R5)Addressing Modes (10)nRegister Indirect Mode (ctd.)Example: Using indirect addressing to access a list of n numbers
40、Addressing Modes (11)nRegister Indirect Mode (ctd.)AdvantagesnIt can reference memory without paying the price of having a full memory address in the instruction.nReduce the memory access times.Addressing Modes (12)nIndirect ModeIndirect addressing through a memory location is also possible, but it
41、is found only in CISC-style processors.The effective address of the operand is the contents of a memory location whose address appears in the instruction.EA = AExample: Add (A), R0Add (A),R0BOperandABAddressing Modes (13)nIndirect Mode (ctd.)AdvantagenThe address space is very large.Memory word leng
42、th N-2N address spaceDisadvantagenInstruction execution requires two memory references to fetch the operand : one to get its address and a second to get its value.Multilevel Indirect AddressingnEA = AnOne bit of a full-word address is an indirect flag (I).If the I bit is 0, then the word contains th
43、e EA.If the I bit is 1, then another level of indirection is invoked. Addressing Modes (14)nIndex ModeX(Ri)The effective address of the operand is generated by adding a constant value to the contents of a register (index register).EA = X + RiX (offset) : the constant value contained in the instructi
44、onThe contents of the index register are not changed in the process of generating the effective address.Addressing Modes (15)nIndex Mode (ctd.)Two Ways of Using the Index ModenOffset is given as a constantAddressing Modes (16)nIndex Mode (ctd.)Two Ways of Using the Index Mode (ctd.)nOffset is in the
45、 index register. This form requires an offset field in the instruction large enough to hold an address.Addressing Modes (17)nIndex Mode (ctd.)UsagenFacilitate access to an operand whose location is defined relative to a reference point within the data structure in which the operand appears.Usage Exa
46、mplenN rows and four columns arrayThe memory is byte addressable and the word length is 32 bits.Addressing Modes (18)nIndex Mode (ctd.)Usage Example (ctd.)Addressing Modes (19)nIndex Mode (ctd.)Variations of index addressingnBase with index(Ri, Rj)A second register ( base register) is used to contai
47、n the offset X.EA = Ri + RjnBase with index and offsetX(Ri, Rj)Use index register, base register and a constant.EA = Ri + Rj + XStacks (1)nA stack is a list of data elements, usually words, with the accessing restriction that elements can be added or removed at one end of the list only.nThe structur
48、e is sometimes referred to as a pushdown stack or last-infirst-out (LIFO) stack.nPushPlace a new item on the stacknPopRemove the top item from the stacknIn modern computers, a stack is implemented by using a portion of the main memory.nProgrammer can create a stack in the memorynThere is often a spe
49、cial processor stack as wellStacks (2)nProcessor StackProcessor has stack pointer (SP) registerthat points to top of the processor stackAssume a byte-addressable memory with a 32-bit word lengthPush operation involves two instructions:SubtractSP, SP, #4StoreRj, (SP)Pop operation also involves two in
50、structions:LoadRj, (SP)AddSP, SP, #4Stacks (3)nProcessorStack (ctd.)Stacks (4)nProcessor Stack (ctd.)Subroutines (1)nIn a given program, a particular task may beexecuted many times using different dataExamples: mathematical function, list sortingnImplement task in one block of instructionsThis is ca
51、lled a subroutinenRather than reproduce entire subroutine block in each part of program, use a subroutine callSpecial type of branch with Call instructionSubroutines (2)nBranching to same block of instructionssaves space in memory, but must branch backThe subroutine must return to calling program af
52、ter executing last instruction in subroutineThis branch is done with a Return instructionnSubroutine LinkageSubroutine can be called from different placesHow can return be done to correct place?nThis is the issue of subroutine linkageSubroutines (3)nSubroutine Linkage (ctd.)During execution of Call
53、instruction, PC updated to point to instruction after CallSave this address for Return instruction to useSimplest method: place address in link registerCall instruction performs two operations: store updated PC contents in link register, then branch to target (subroutine) addressReturn just branches
54、 to address in link registerSubroutines (4)nSubroutine Linkage (ctd.)Subroutines (5)nSubroutine Nesting & The Processor StackWe can permit one subroutine to call another, which results in subroutine nesting.Link register contents after first subroutine call are overwritten after second subroutine ca
55、ll.First subroutine should save link register on the processor stack before second call.After return from second subroutine, first subroutine restores link register.Subroutine nesting can be carried out to any depth.Return addresses are generated and used in a last-infirst-out order. This suggests t
56、hat the return addresses associated with subroutine calls should be pushed onto the processor stack.n2.8 Additional InstructionsLogic InstructionsShift and Rotate InstructionsMultiplication and DivisionAdditional Instructions (1)nLogic InstructionsAND, OR, and NOT operations on single bitsare basic
57、building blocks of digital circuits.Similar operations in software on multiple bits.Using RISC-style instructions, all operands arein registers or specified as immediate values:Or R4, R2, R3And R5, R6, #0xFFn8-bit immediate is zero-extended to 32 bitsAdditional Instructions (2)nLogic Instructions (c
58、td.)Suppose that four ASCII characters are contained in the 32-bit register R2. In some task, we wish to determine if the rightmost character is Z. The ASCII code for Z is 01011010, which is expressed in hexadecimal notation as 5A.nAnd R2, R2, #0xFFnMove R3, #0x5AnBranch_if_R2=R3 FOUNDZAdditional In
59、structions (3)nShift and Rotate Instructions Shifting binary value left/right = mult/div by 2Logical ShiftsnFor general operands, we use a logical shift.nLogic Shifting Left (LShiftL)LShiftL Ri, Rj, countShift the contents of register Rj left by a number of bit positions given by the count operand,
60、and places the result in register Ri, without changing the contents of Rj.nLogic Shifting Right (LShiftR)Additional Instructions (4)nShift and Rotate Instructions (ctd.)Logical Shifts (ctd.)Additional Instructions (5)nShift and Rotate Instructions (ctd.)Digit-Packing ExamplenIllustrate shift, logic,
61、 byte-access instructionsnMemory has two binary-coded decimal digitsnPointer set to 1st byte for index-mode access to load 1st digit, which is shifted to upper bitsnUpper bits of 2nd digit are cleared by ANDingnORing combines 2nd digit with shifted 1st digit for result of two packed digits in a sing
62、le byten32-bit registers, but only 8 lowest bits relevantAdditional Instructions (6)nShift and Rotate Instructions (ctd.)Digit-Packing Example (ctd.)Additional Instructions (7)nShift and Rotate Instructions (ctd.)Arithmetic ShiftsnIn an arithmetic shift, the bit pattern being shifted is interpreted
63、as a signed number.nOn a right shift the sign bit must be repeated as the fill-in bit for the vacated position as a requirement of the 2s-complement representation for numbers.Additional Instructions (8)nShift and Rotate Instructions (ctd.)Rotate OperationsnRotate left without carryAdditional Instru
64、ctions (9)nShift and Rotate Instructions (ctd.)Rotate Operations (ctd.)nRotate left with carryAdditional Instructions (10)nShift and Rotate Instructions (ctd.)Rotate Operations (ctd.)nRotate right without carryAdditional Instructions (11)nShift and Rotate Instructions (ctd.)Rotate Operations (ctd.)n
65、Rotate right with carryAdditional Instructions (12)nMultiplication and DivisionSigned integer multiplication of n-bit numbers produces a product with as many as 2n bitsProcessor truncates product to fit in a register:MultiplyRk, Ri, Rj(Rk Ri Rj)For general case, 2 registers (Rk and R(k+1)may hold re
66、sultInteger division produces quotient as result:Divide Rk, Ri, Rj (Rk Ri / Rj)Remainder is discarded or placed in a register R(k+1)n2.10 CISC Instruction SetsAdditional Addressing ModesCondition CodesCISC Instruction Sets (1)nCISC instruction sets are not constrained to the load/store architecture,
67、 in which arithmetic and logic operations can be performed only on operands that are in processor registers.nCISC instructions do not necessarily have to fit into a single word. Some instructions may occupy a single word, but others may span multiple words.nMost arithmetic and logic instructions use
68、 the two-address format.Operation destination, sourceExample: Add B, AnPerforms the operation B A + B on memory operands.CISC Instruction Sets (2)nThe Move instruction includes the functionality of the Load and Store instructionsMove destination, sourceExample C = A + BnMove C, BnAdd C, AIn some CIS
69、C processors one operand may be in the memory but the other must be in a register.nMove Ri, AnAdd Ri, BnMove C, RiCISC Instruction Sets (3)nAutoincrement and Autodecrement ModeAutoincrement ModenThe effective address of the operand is the contents of a register specified in the instruction. After ac
70、cessing the operand, the contents of this register are automatically incremented to point to the next item in a list.n(Ri)+nEA = Ri Increment RinUseful for adjusting pointers in loop body:Add SUM, (Ri)MoveByte(Rj), RkIncrement by 4 for words, and by 1 for bytesCISC Instruction Sets (4)nAutoincrement
71、 and Autodecrement Mode (ctd.)Autodecrement ModenThe contents of a register specified in the instruction are first automatically decremented and are then used as the effective address of the operand.n(Ri)nUse autoinc. & autodec. for stack operations:Move (SP), NEWITEM (push)Move ITEM, (SP)(pop)CISC
72、Instruction Sets (5)nRelative ModeThe effective address is determined by the Index mode using the program counter in place of the general-purpose register Ri.EA = PC + X, X is a signed numberUsagenAccess data operandnSpecify the target address in branch instructions.Example Branch 0 LoopThe branch t
73、arget location can be computed by specifying it as an offset from the current value of the program counter.CISC Instruction Sets (6)nCondition CodesProcessor can maintain information on results to affect subsequent conditional branchesResults from arithmetic/comparison & MoveCondition code flags in
74、a status register: N (negative) 1 if result negative, else 0 Z (zero) 1 if result zero, else 0 V (overflow) 1 if overflow occurs, else 0 C (carry) 1 if carry-out occurs, else 0CISC Instruction Sets (7)nBranches Using Condition CodesCISC branches check condition code flagsFor example, decrementing a
75、register causes N and Z flags to be cleared if result is not zeroA branch to check logic condition N Z 0:Branch0LOOPOther branches test conditions for , , , , Also Branch_if_overflow and Branch_if_carryConsider CISC-style list-summing program (next page)CISC Instruction Sets (8)nBranches Using Condi
76、tion Codes (ctd.)CISC Instruction Sets (9)nBranches Using Condition Codes (ctd.)RISC and CISC Styles (1)nRISC characteristics include:Simple addressing modesAll instructions fitting in a single wordFewer total instructionsArithmetic/logic operations on registersLoad/store architecture for data trans
77、fersMore instructions executed per programnSimpler instructions make it easier todesign faster hardware (e.g., use of pipelining)RISC and CISC Styles (2)nCISC characteristics include:More complex addressing modesInstructions spanning more than one wordMore instructions for complex tasksArithmetic/lo
78、gic operations on memory Memory-to-memory data transfersFewer instructions executed per programnComplexity makes it somewhat more difficult to design fast hardware, but still possibleRISC and CISC Styles (3)nBefore the 1970s, all computers were of CISC type. Move the complexity from the software lev
79、el to the hardware level.nRISC-style designs emerged as an attempt to achieve very high performance by making the hardware very simple.nTodays processors often exhibit what may seem to be a compromise between these approaches.Pentium 4 Example (1)nOperating ModeReal mode all features added since the
80、 8088 are turned off (effectively behaves like a simple 8088; if a program does something wrong whole machine crashes)Virtual 8086 mode makes it possible to run old 8088 programs in a protected way (if a program crashes, the OS is notified instead of the machine crashing)Protected mode actually beha
81、ves like a Pentium 4!n4 levels: 0- kernel, 3-user, 1, 2, rarely used.Pentium 4 Example (2)nAddress Space16,384 segmentsEach segment has 232 addresses (4 GB)Most operating systems, including Unix and Windows, support only one segmentEvery byte has its own addressWords are 32 bits long, and little-end
82、ianPentium 4 Example (3)nPrimary RegistersPentium 4 Example (4)nPrimary Registers (ctd.)EAX, EBX, ECX and EDXnEAX is the main arithmetic register.nEBX is good for holding pointersnECX plays a role in loopingnEDX is needed for multiplication and division (holding half of the 64-bit products and divid
83、ends)nThese registers contain 8- and 16-bit registers in the low-order bits for manipulation of 8- and 16-bit quantities, respectively.Pentium 4 Example (5)n Primary Registers (ctd.)ESI, EDI, EBP and ESP nESI source string pointernEDI destination string pointernEBP base of the current stack framenES
84、P stack pointerEIP and EFLAGSnEIP instruction pointernEFLAGS PSW CS, SS, DS, ES, FS, GSnSegment RegisternLeftover from the 8088 generationPentium 4 Example (6)nData TypesTwos complement integersUnsigned integersBinary coded decimal numbersIEEE 754 floating point numbersPentium 4 Example (7)nInstruct
85、ion FormatPentium 4 Example (8)nInstruction Format (ctd.)PREFIX (0 5 bytes)nAn extra opcode stuck onto the front of an instruction to change its action.OPCODE (1 2 bytes)nThe use of the low-order bit in some instructions to indicate byte/word.nThe use of adjoining bit to indicate whether the memory
86、address is the source or the destination.n0xFF is designated as an escape code to permit a second instruction byte.Pentium 4 Example (9)nInstruction Format (ctd.)MODE (0 1 bytes)nMOD field (2 bits): Means that there are only 4 ways to address operands and one of the operands must always be a registe
87、r.nREG (3 bits)nR/M (3 bits)SIB (0 1 bytes) nSome modes require an additional byte, giving a further specification.DISPLACEMENT (0 4 bytes) IMMEDIATE (0 4 bytes)Pentium 4 Example (10)nAddressing Mode (32-bit mode)Immediate, Direct, Register, Register Indirect ModeBase with Displacement ModenExample:
88、 MOV EAX, EBP+60100060 = displacement1000doubleword1060OperandMainmemoryaddressBase register EBPOperand address (EA) = EBP + 60(a) Base with displacement mode, expressed as EBP + 60*Pentium 4 Example (11)nAddressing Mode (32-bit mode)Index with Displacement ModeBase with Index ModeBase with Index an
89、d Displacement ModenExample: MOV EAX, EBP + ESI*4 + 2001000200 = displacement10001200OperandBase register EBPOperand address (EA) = EBP + ESI 4 + 200(b) Base with displacement and index mode, expressed as EBP + ESI * 4 + 2001360List of 4-byte (double word) data items40Index register ESIscale factor
90、= 4160 = Index register 4*Pentium 4 Example (12)nAddressing Mode (32-bit mode)The MODE byte in Pentium 4s instruction format controls the addressing modesnOne of the operand is always specified in a register, and is given by the value of the REG field.nThe other operand is specified by the combinati
91、on of the MOD and R/M fields.Pentium 4 Example (13)nAddressing Mode (32-bit mode) (ctd.)MOD= 01nIf an 8-bit offset is selected, it is first sign-extended to 32-bits before being added.MOD=11nFor word instructions, the first choice is used; for byte instructions, the second choice is used.SIBnWhen a
92、SIB byte is present, the operand address is computed by multiplying the index register by 1,2,4,or 8 (depending on SCALE), adding it to the base register, and finally possibly adding an 8- or 32-bit displacement, depending on MOD.Pentium 4 Example (14)nAddressing Mode (32-bit mode) (ctd.)Summary (1)
93、nInstruction FormatsInstruction RepresentationCommon Instruction Address Field FormatsnZero-address Instruction nOne-address instruction nTwo-address instruction nThree-address instructionInstruction lengthOpcode format (expanding opcode) Summary (2)nAddressing ModesDefinition: The different ways in
94、 which the location of an operand is specified in an instruction are referred to as addressing modes.Typical Addressing ModesnImmediate mode nDirect mode (Absolute mode) nRegister mode nIndirect modenRegister indirect mode nIndex mode nRelative mode nAutoincrement modenAutodecrement modeSummary (3)nRISC CharacteristicsnCISC Characteristics
