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1、Chapter 2 Machine Instruction2Contentsl2.1 Instruction and Instruction Sequencing l2.2 Instruction Formatsl2.3 Addressing Modesl2.4 Stacksl2.5 Subroutinesl2.6 Additional Instructionsl2.7 CISC Instruction Setsl2.8 RISC and CISC Styles2.1 Instruction and Instruction SequencinglRegister Transfer Notati
2、onlAssembly-Language NotationlRISC and CISC Instruction SetslIntroduction to RISC Instruction SetslInstruction Execution and Straight-Line SequencinglBranching32.1 Instruction and Instruction SequencinglFour Types of InstructionslData transfers between the memory and the processor registerslArithmet
3、ic and logic operations on datalProgram sequencing and controllI/O transfers4Register Transfer NotationlRegister transfer notation is used to describe hardware-level data transfers and operationslProcessor register: R0, R5lI/O register: DATAIN, OUTSTATUSlMemory location: LOC, PLACE, A, VAR2lUse to d
4、enote contents of a location Use to denote transfer to a destination5Register Transfer NotationlExample1: R2 LOClTransfer from LOC in memory to register R2lRight-hand expression always denotes a value, left-hand side always names a locationlExample2: R4 R2 R3lAdd the contents of registers R2 and R3,
5、 place the sum in register R46Assembly-Language NotationlRTN shows data transfers and arithmeticlAnother notation needed to representmachine instructions & programs using themlAssembly language is used for this purposelFor the two preceding examples using RTN,the assembly-language instructions are:L
6、oad R2, LOCAdd R4, R2, R37Assembly-Language NotationlAn instruction specifies the desired operation and the operands that are involvedlExamples in this chapter will use English words for the operations (e.g., Load, Store, and Add)lCommercial processors use mnemonics,usually abbreviations (e.g., LD,
7、ST, and ADD)lMnemonics differ from processor to processor8RISC and CISC Instruction SetslNature of instructions distinguishes computerlTwo fundamentally different approacheslReduced Instruction Set Computers (RISC) have one-word instructions and require arithmetic operands to be in registerslSmall s
8、et of instructions (typically 32)lSimple instructions, each executes in one clock cyclelEffective use of pipelininglExample: ARM9RISC and CISC Instruction SetslNature of instructions distinguishes computerlTwo fundamentally different approacheslComplex Instruction Set Computers (CISC)have multi-word
9、 instructions and allow operands directly from memorylMany instructions (several hundreds)lAn instruction takes many cycles to executelExample: Intel Pentium10RISC Instruction SetslTwo key characteristics of RISC instruction setslEach instruction occupies a single wordlA load/store architecture is u
10、sed, meaning:lOnly Load and Store instructions are used to access memory operandslOperands for arithmetic/logic instructions must be in registers, or one of them may be given explicitly in instruction word11RISC Instruction SetslInstructions/data are stored in the memorylBecause RISC requires regist
11、er operands,data transfers are required before arithmeticlThe Load instruction is used for this purpose:Load procr_register, mem_locationlAddressing mode specifies memory location;different modes are discussed later12RISC Instruction SetslConsider high-level language statement:C A BlA, B, and C corr
12、espond to memory locationslRTN specification with these symbolic names:C A BlSteps: fetch contents of locations A and B,compute sum, and transfer result to location C13RISC Instruction SetslSequence of simple RISC instructions for task:Load R2, ALoad R3, BAdd R4, R2, R3Store R4, ClLoad instruction t
13、ransfers data to registerlStore instruction transfers data to the memorylDestination differs with same operand order14Instruction Execution and Straight-Line SequencinglExample:C = A + BC A + BlAssume thatlThe word length is 32 bitslThe memory is byte-addressablelA desired memory address can be dire
14、ctly specified in Load and Store instructions.15Instruction Execution and Straight-Line SequencinglStraight-line sequencing:PC = iPC = i + 4lInstruction FetchlInstruction Execute16BranchinglAdding a list of n numberslSeparate Load and Add Instructions 17BranchinglAdding a list of n numberslA program
15、 looplBranch InstructionslLoad a new address into the PClBranch TargetlConditional BranchlCompare the contents of tworegisters Branch_if_R4R5 LooplCondition Codes 18192.2 Instruction FormatslWhats Machine Instruction? lThe instructions which specify the actions that must be performed by the processo
16、r circuitry to carry out the desired tasks.lMachine codelBinarylUsually represented by assembly codeslWhats Instruction Set?lThe collection of different machine instructions that the processor can execute. 20lElements of a Machine Instruction lOperation code (Opcode)lSpecify the operation to be perf
17、ormed (e.g., ADD, I/O), expressed as a binary code.lSource operand referencelOperands required for the instruction are specified.lResult operand referencelWhere should the result of the operation be placed?lSource and result operands can be in one of three areasMain or virtual memoryProcessor regist
18、erI/O device21lElements of a Machine Instruction lNext instruction referencelHow / Where is the next instruction to be found?In most cases, this is not explicitly stated in the instruction.Next instruction is the one that logically follows the current one in the program (sequential / linear progress
19、ion through the program).22lInstruction Representation lWithin the computer, each instruction is represented by a sequence of binary bits.lThe instruction is divided into two fieldslOperation code fieldSpecify the operation to be performedlAddress fieldlInstruction Design CriterialShort instructions
20、 are better than long oneslSufficient room in the instruction format to express all the operations desiredlNumber of bits in the address field23lInstruction Address Field Formats lZero-address InstructionlOne-address InstructionlOP A AlAC OP A ACTypically, it is understood implicitly that a second o
21、perand is in the accumulator of the processor.24lInstruction Address Field Formats lTwo-address InstructionlA1 OP A2 A1A1: Destination operand addressA2: Source operand addresslThree-address InstructionlA2 OP A3 A125lInstruction Length lFixed length: All instructions have the same lengthlVariable le
22、ngth: Instructions may be many different lengths26lInstruction Length lMethods to reduce instruction lengthlIf the operand is to be used several times, it can be moved into a register. (Note: If an operand is to be used only once, putting it in a register is not worth it.)lSpecify one or more operan
23、ds implicitly.27lOpcode Format lFixed-length OpcodelThe Opcode length is fixed, but the instruction length is variable. lSuppose that, k bits opcode, n bits operand addressAllows for 2k different operationsAllows for 2n addressable memory cells28lOpcode Format lVariable-length Opcode (Expanding Opco
24、de)lUsually, the instruction length is fixed, and the length of Opcode and operand address is limited each other.lExample: Instruction length is 16-bit, operand address is 4-bit.This might be reasonable on a machine that has 16 registers on which all arithmetic operations take place.One design would
25、 be a 4-bit opcode and three addresses in each instruction, giving 16 three-address instructions.29lOpcode Format lVariable-length Opcode (Expanding Opcode)lExample: Instruction length is 16-bit, operand address is 4-bit. (ctd.)Suppose the designers need15 three-address instructions14 two-address in
26、structions31 one-address instructions16 zero-address instructionsHow should we design the instruction format?30lOpcode Format lVariable-length Opcode (Expanding Opcode)lExample: Instruction length is 16-bit, operand address is 4-bit. (ctd.)15 three-address instructions4-bit opcode 0000 1110 (1512 bi
27、t)31lOpcode Format lVariable-length Opcode (Expanding Opcode)lExample: Instruction length is 16-bit, operand address is 4-bit. (ctd.)14 two-address instructions8-bit opcode 11110000 11111101 (158 bit)32lOpcode Format lVariable-length Opcode (Expanding Opcode)lExample: Instruction length is 16-bit, o
28、perand address is 4-bit. (ctd.)31 one-address instructions12-bit opcode 1111 11110 0000 1111 1111 1110 (154 bit)33lOpcode Format lVariable-length Opcode (Expanding Opcode)lExample: Instruction length is 16-bit, operand address is 4-bit. (ctd.)16 zero-address instructions16-bit opcode 111111111111 00
29、00 111111111111 1111 34lOpcode Format lVariable-length Opcode (Expanding Opcode)lSummary Expanding Opcodes demonstrates a trade-off between space for Opcode and space for other information.Carrying variable Opcode to an extreme, it is possible to minimize the average instruction length by encoding e
30、very instruction to minimize bits needed. However, this will result in instructions of various sizes that are not aligned on byte boundaries.Expanding Opcodes is typically employed at the byte level like the above example.352.3 Addressing ModeslAddressing Modes lHow to specify where an operand for a
31、n instruction is located?lHow the bits of an address field in an instruction are interpreted?lWhat is Addressing Modes?lThe different ways in which the location of an operand is specified in an instruction are referred to as addressing modes.36lTypical Addressing Modes 37lImmediate mode lThe operand
32、 is given explicitly in the instruction.lExample: Add R4, R6, #200lUsagelDefine and use constantslSet initial values of variableslAdvantagelNo memory reference other than the instruction fetch is required to obtain the operand.lDisadvantagelOnly a constant can be supplied this way.lThe size of the n
33、umber is limited by the size of the address field.OPOperand38lAbsolute modelThe operand is in a memory location; the address of this location is given explicitly in the instruction.lExample: Load R2, NUM1lEA=AlEA: Actual (Effective) address of the location containing the referenced operandlA: conten
34、ts of an address field in the instructionlNotelIn a system without virtual memory, the effective address will be either a main memory address or a register address.lIn a virtual memory system, the effective address is a virtual address or a register address.39lAbsolute mode (ctd.)lUsagelAccess globa
35、l variables whose address is known at compile time.lAdvantagelOnly one memory reference and no special calculation.lDisadvantagelThe instruction will always access exactly the same memory location.lIt provides only a limited address space.40lRegister modelThe operand is the contents of a processor r
36、egister; the address of the register is given in the instruction.lEA = RilRi: contents of an address field in the instruction thatrefers to a register.lExample: Add R4, R2, R3lUsagelAccess variables which areaccessed most often.41lRegister mode (ctd.) lAdvantagelOnly a small address field is needed
37、in an instruction.lNo memory reference references are required.lDisadvantagelThe address space is very limited.42lRegister Indirect mode lThe effective address of the operand is the contents of a register whose address appears in the instruction.lEA = Ri43lRegister Indirect mode (ctd.) lExample: Loa
38、d R2, (R5)44lRegister Indirect mode (ctd.) lExample: Using indirect addressing to access a list of n numbersFigure 2.8 Use of indirect addressing in the program of Figure 2.645lRegister Indirect mode (ctd.)lAdvantagelIt can reference memory without paying the price of having a full memory address in
39、 the instruction.lReduce the memory access times.46lIndirect mode lIndirect addressing through a memory location is also possible, but it is found only in CISC-style processors.lThe effective address of the operand is the contents of a memory location whose address appears in the instruction.lEA = A
40、lExample: Add (A), R0Add (A),R0BOperandAB47lIndirect mode (ctd.)lAdvantagelThe address space is very large.lIf memory word length is N, then 2N address spacelDisadvantagelInstruction execution requires two memory references to fetch the operand: one to get its address and a second to get its value.l
41、Multilevel indirect addressinglEA = AlOne bit of a full-word address is an indirect flag (I).If the I bit is 0, then the word contains the EA.If the I bit is 1, then another level of indirection is invoked.48lIndexed mode lX(Ri)lThe effective address of the operand is generated by adding a constant
42、value to the contents of a register (index register).lEA = X + RilX (offset): the constant value contained in the instructionlNotelThe contents of the index register are not changed in the process of generating the effective address.49lIndexed mode (ctd.)lTwo ways of using the index modelOffset is g
43、iven as a constantExample50lIndexed mode (ctd.)lTwo ways of using the index modelOffset is in the index register. This form requires an offset field in the instruction large enough to hold an address.Example51lIndexed mode (ctd.)lUsagelFacilitate access to an operand whose location is defined relati
44、ve to a reference point within the data structure in which the operand appears.lExample: N rows and four columns arraylThe memory is byte addressable and the word length is 32 bits52lIndexed mode (ctd.)lUsagelExample53lIndexed Addressing (ctd.)lVariations of indexed addressing modelBase with index(R
45、i, Rj)A second register (base register) is used to contain the offset X.EA = Ri + RjlBase with index and offsetX(Ri, Rj)Use index register, base register and a constant.EA = Ri + Rj + X542.4 StackslA stack is a list of data elements, usually words, with the accessing restriction that elements can be
46、 added or removed at one end of the list only.lThe structure is sometimes referred to as a pushdown stack or last-infirst-out (LIFO) stack.lPush: Place a new item on the stacklPop: Remove the top item from the stacklIn modern computers, a stack is implemented by using a portion of the main memory.lP
47、rogrammer can create a stack in the memorylThere is often a special processor stack as well55lProcessor stacklProcessor has stack pointer (SP) register that points to top of the processor stack.lAssume a byte-addressable memory with a 32-bit word lengthlPush operation involves two instructions:Subtr
48、actSP, SP, #4StoreRj, (SP)lPop operation also involves two instructions:LoadRj, (SP)AddSP, SP, #456lProcessor stack57lProcessor stack582.5 SubroutineslIn a given program, a particular task may be executed many times using different datalExamples: mathematical function, list sortinglImplement the tas
49、k in one block of instructionslThis is called a subroutinelRather than reproduce entire subroutine block in each part of program, use a subroutine calllSpecial type of branch with Call instruction592.5 SubroutineslBranching to same block of instructions saves space in memory, but must branch backlTh
50、e subroutine must return to calling program after executing last instruction in subroutinelThis branch is done with a Return instruction60lSubroutine LinkagelSubroutine can be called from different placeslHow can return be done to correct place?lThis is the issue of subroutine linkagelDuring executi
51、on of Call instruction, PC updated to point to instruction after CalllSave this address for Return instruction to uselSimplest method: place address in link registerlCall instruction performs two operations: store updated PC contents in link register, then branch to target (subroutine) addresslRetur
52、n just branches to address in link register61lSubroutine Linkage62lSubroutine Nesting & The Processor StacklWe can permit one subroutine to call another, which results in subroutine nesting.lLink register contents after first subroutine call are overwritten after second subroutine call.lFirst subrou
53、tine should save link register on the processor stack before second call. lAfter return from second subroutine, first subroutine restores link register.lSubroutine nesting can be carried out to any depth. lReturn addresses are generated and used in a last-infirst-out order. This suggests that the re
54、turn addresses associated with subroutine calls should be pushed onto the processor stack.632.6 Additional InstructionslLogic InstructionslAND, OR, and NOT operations on single bitsare basic building blocks of digital circuits.lSimilar operations in software on multiple bits.lUsing RISC-style instru
55、ctions, all operands arein registers or specified as immediate values:Or R4, R2, R3And R5, R6, #0xFFl16-bit immediate is zero-extended to 32 bits64lLogic InstructionslSuppose that four ASCII characters are contained in the 32-bit register R2. In some task, we wish to determine if the rightmost chara
56、cter is Z. The ASCII code for Z is 01011010, which is expressed in hexadecimal notation as 5A.lAnd R2, R2, #0xFFlMove R3, #0x5AlBranch_if_R2=R3 FOUNDZ65lShift and Rotate InstructionslShifting binary value left/right = mult/div by 2lLogical ShiftslFor general operands, we use a logical shift.lLogic S
57、hifting Left (LShiftL)LShiftL Ri, Rj, countShift the contents of register Rj left by a number of bit positions given by the count operand, and places the result in register Ri, without changing the contents of Rj.lLogic Shifting Right (LShiftR)66lShift and Rotate Instructions67lShift and Rotate Inst
58、ructionslDigit-Packing ExamplelIllustrate shift, logic, byte-access instructionslMemory has two binary-coded decimal (BCD) digitslPointer set to 1st byte for index-mode access to load 1st digit, which is shifted to upper bitslUpper bits of 2nd digit are cleared by ANDinglORing combines 2nd digit wit
59、h shifted 1st digit for result of two packed digits in a single bytel32-bit registers, but only 8 lowest bits relevant68lShift and Rotate InstructionslDigit-Packing Example69lShift and Rotate InstructionslArithmetic shiftslIn an arithmetic shift, the bit pattern being shifted is interpreted as a sig
60、ned number. lOn a right shift the sign bit must be repeated as the fill-in bit for the vacated position as a requirement of the 2s-complement representation for numbers.70lShift and Rotate InstructionslRotate operationslRotate left without carry 71lShift and Rotate InstructionslRotate operationslRot
61、ate left with carry 72lShift and Rotate InstructionslRotate operationslRotate right without carry 73lShift and Rotate InstructionslRotate operationslRotate right with carry 74lMultiplication and Division InstructionslSigned integer multiplication of n-bit numbers produces a product with as many as 2
62、n bitslProcessor truncates product to fit in a register:Multiply Rk, Ri, Rj(Rk Ri Rj)lFor general case, 2 registers (Rk and R(k+1) may hold resultlInteger division produces quotient as result:Divide Rk, Ri, Rj(Rk Ri / Rj)lRemainder is discarded or placed in a register R(k+1)752.7 CISC Instruction Se
63、tslCISC instruction sets are not constrained to the load/store architecture, in which arithmetic and logic operations can be performed only on operands that are in processor registers.lCISC instructions do not necessarily have to fit into a single word. Some instructions may occupy a single word, bu
64、t others may span multiple words.lMost arithmetic and logic instructions use the two-address format.lOperation destination, sourcelE.g., Add B, Alperforms the operation B A + B on memory operands.76lThe Move instruction includes the functionality of the Load and Store instructions.lMove destination,
65、 sourcelExample C = A + B (all three operands may be in memory)lMove C, BlAdd C, AlIn some CISC processors one operand may be in the memory but the other must be in a register.lMove Ri, AlAdd Ri, BlMove C, Ri77lAutoincrement and Autodecrement ModelAutoincrement modelThe effective address of the oper
66、and is the contents of a register specified in the instruction. After accessing the operand, the contents of this register are automatically incremented to point to the next item in a list.l(Ri)+lEA = Ri Increment RilUseful for adjusting pointers in loop body:Add SUM, (Ri)MoveByte(Rj), RklIncrement
67、by 4 for words, and by 1 for bytes78lAutoincrement and Autodecrement ModelAutodecrement modelThe contents of a register specified in the instruction are first automatically decremented and are then used as the effective address of the operand.l(Ri)lDecrement Ri EA = RilUse autoinc. & autodec. for st
68、ack operations:Move (SP), NEWITEM (push)Move ITEM, (SP)(pop)79lRelative ModelThe effective address is determined by the Index mode using the program counter in place of the general-purpose register Ri.lEA = PC + XlX is a signed numberlUsageAccess data operandSpecify the target address in branch inst
69、ructionsExample: Branch 0 LoopThe branch target location can be computed by specifying it as an offset from the current value of the program counter.80lCondition CodeslProcessor can maintain information on results to affect subsequent conditional brancheslResults from arithmetic/comparison & MovelCo
70、ndition code flags in a status register: N (negative) 1 if result negative, else 0 Z (zero) 1 if result zero, else 0 V (overflow) 1 if overflow occurs, else 0 C (carry) 1 if carry-out occurs, else 081lBranches Using Condition CodeslCISC branches check condition code flagslFor example, decrementing a
71、 register causes N and Z flags to be cleared if result is not zero lA branch to check logic condition N Z 0:Branch0LOOPlOther branches test conditions for , , , , lAlso Branch_if_overflow and Branch_if_carrylConsider CISC-style list-summing program82lBranches Using Condition Codes832.8 RISC and CISC
72、 StyleslRISC characteristics include: lsimple addressing modeslall instructions fitting in a single wordlfewer total instructionslarithmetic/logic operations on registerslload/store architecture for data transferslmore instructions executed per programlSimpler instructions make it easier todesign fa
73、ster hardware (e.g., use of pipelining)84lCISC characteristics include: lmore complex addressing modeslinstructions spanning more than one wordlmore instructions for complex taskslarithmetic/logic operations on memory lmemory-to-memory data transferslfewer instructions executed per programlComplexit
74、y makes it somewhat more difficult to design fast hardware, but still possible85lSummarylInstruction and instruction sequencinglAssembly-language NotationlRISC instruction setslInstruction ExecutionStraight-Line Sequencing and BranchinglInstruction FormatslInstruction RepresentationlCommon Instructi
75、on Address Field FormatsZero-, One-, Two-, and Three-address InstructionlOpcode Format (Expanding Opcode)86lSummary (ctd.)lAddressing ModeslThe different ways in which the location of an operand is specified in an instruction.lTypical RISC Addressing ModeslStack and SubroutinelAdditional instruction
76、slLogical, Shift & Rotate, Multiplication and Division InstructionslCISC instruction setslAutoincrement, Autodecrement and Relative modelCondition CodeslRISC vs. CISC styles87lHomework l2.4, 2.9lAssume that a computers instruction length is 16-bit, and its operand address is 6-bit. Suppose the desig
77、ners need two-address instructions, one-address instructions and zero-address instructions. How should we design the instruction format? And specify the numbers of each type of instruction can be designed.lAssume that a computers word-length is 16-bit, the capacity of main memory is 64K words. If it employs single-word-length one-address instructions and contains 64 instructions. Design an instruction format with addressing modes of direct, indirect, index, and relative.
