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1、总思卡尔XS128系列（二）PLL锁郴坏通俗点说，设SPLL锁和环就相当丁超频，单片机超频的原因和PC机足一个逍理。分频的主要原 因圧外设需要的工作频率往往远低丁 CPU/MEMORY,这也和PC机南北桥的原理类似.相对来说，PLL锁相环的设置还是比较简单的，【火I为东芮很死，完全可以照搬.只是大家也不要太 矢 设置太高相对來说不够稳泄.进行过PC机超频的应该很存体会，一般我们现任用的XS128我觉得设 置在80MHz足比较介适的 *11比帕几届比处用的DG128这个频率已经蛮高的了。还冇就SYNR.REFDV 只有在CLKSEL_PLLSEL=O的惜况下才能写入，不过这足系统默认状态.爹半大
2、家可能还会有以下儿点疑间：1.PLL锁相环怎么设直？答：通过写REFDV（CRG参考分频寄存器）和SYNR （CRG介成器寄存器）进行设置2代码里while（!CRGFLG_LOCK）;这句危什么的？答：时钟校正同步3 一为什么代码中会有多多少少的几句空语句？答：锁相环从设定到帰后稳定还圧需要一点点时间的，所以需要加几条空指令Code Warrior 5.0Target: MC9S12XS128Crystal: 16.000Mhzcommon defines and macros */ /* derivative information */ mc9sl2xsl28include /*incl
3、ude pragma LINK_INF0 DERIVATIVE void delayms(int ms)丄int 11,jj；if (msl) ms=l;for (ii=0;iims;ii+)/40MHz1msfor(jj=0;jj3338;jj+);/ disengage PLL to system / turn on PLLVC0FRQ7:6;SYNDIV5:0CLKSEL=OXOO;PLLCTL_PLLON=1;SYNR二0x00 | 0x01;void SetBusCLK_16M(void)/ VCO= 2*fOSC*(SYNDIV + 1)/(REFDIV + 1) / fPLL=
4、fVCO/ (2 X POSTDIV)/ fBUS= fPLL/2/ VCOCLK Frequency RangesVC0FRQ7:600/ 48MHz fVCO = 80MHz01/ Reserved10/ 80MHz fVCO = 120MHz11REFDV=0x80 | 0x01;REFFRQ7:6;REFDIV5:0POSTDIV二0x00;/ 1MHz = fREF =2MHz6MHz0001/ 2MHzfREF =/6MHzfREF12MHz11/ fREF二fOSC/(REFDIV + 1)/ REFCLK Frequency Ranges REFFRQ7:6/ pllclock
5、=2*osc*(1+SYNR)/(1+REFDV)=32MHz;/ 4:0, fPLL= fVCO/(2xPOSTDIV)/ If POSTDIV = $00 then fPLL is identical to fVCO(divide by one)._asm(nop):/ BUS CL0CK=16M_asm(nop);wh订e(! (CRGFLG_LOCK=1);/when pll is steady ,then use it;CLKSEL PLLSEL =1;void SetBusCLK_32M(void) _CLKSEL=0X00;PLLCTL_PLLON=1;SYNR 二0x40 |
6、0x03;/REFDV=0x80 | 0x01;/engage PLL to system;/ disengage PLL to system/ turn on PLLpllclock=2*osc*(1+SYNR)/(1+REFDV)二64MHz;/ 32MHz = fVCO = 48MHzPOSTDIV二0x00;_asm(nop);/ BUS CL0CK=32M_asm(nop);/disengage PLL to system /turn on PLLwh订e(!(CRGFLG_LOCK=1); CLKSEL.PLLSEL =1;void SetBusCLK_40M(void) CLKS
7、EL=0X00;PLLCTL_PLLON=1;SYNR =0xc0 | 0x04;REFDV=0x80 | 0x01;/when pll is steady , then use it /engage PLL to system;POSTDIV二0x00;/pllclock=2*osc*(1+SYNR)/(1+REFDV)=80MHz;_asm(nop):/BUS CL0CK=40M_asm(nop);whi.1 e(! (CRGFLG_LOCK=1) ;/when pll is steady , then use it;void SetBusCLK_48M(void)CLKSEL二0X00;
8、PLLCTL_PLLON=1；/disengage PLL to system /turn on PLLSYNR 二OxcO | 0x05;REFDV二0x80 | 0x01;CLKSEL.PLLSEL =1; /engage PLL to system;POSTDIV二0x00;/pllclock=2*osc*(l+SYNR)/(l+REFDV)二96MHz;_asm(nop); _asm(nop);/BUS CL0CK=48M/disengage PLL to system /turn on PLLwhile(! (CRGFLG_LOCK=1); CLKSEL_PLLSEL =1;void
9、 SetBusCLK_64M(void) CLKSEL=OXOO;PLLCTL_PLLON=1;SYNR =0xc0 | 0x07;REFDV二0x80 | 0x01;/ when pll is steady ,then use it /engage PLL to system;POSTDIV二0x00;/pllclock=2*osc*(l+SYNR)/(l+REFDV)=128MHz;_asm(nop);/BUS CL0CK=64M/ dPLL to system/turn on PLL_asm(nop);wh订e(!(CRGFLG_LOCK=1); CLKSEL_PLLSEL =1;voi
10、d SetBusCLK_80M(void) CLKSEL=0X00;PLLCTL_PLLON=1;SYNR =0xc0 | 0x09;REFDV二0x80 | 0x01;/when pll is steady , then use it; /engage PLL to system;asm(nop);/BUS CL0CK=80MPOSTDIV二0x00;asm(nop);/when pll is steady ,then use it; /engage PLL to system;/disengage PLL to system /turn on PLL/pllclock=2*osc*(l+S
11、YNR)/(l+REFDV)=160MHz;while(! (CRGFLG_LOCK=1); CLKSEL_PLLSEL =1;void SetBusCLK_88M(void)CLKSEL=0X00;PLLCTL_PLLON=1;SYNR =0xc0 0x0a;REFDV二0x80 | 0x01;POSTDIV二0x00;_asm(nop);_asm(nop);wh订e(! (CRGFLG_LOCK=1); CLKSEL.PLLSEL =1;void SetBusCLK_96M(void)/BUSCLOCK二88M/when pll is steady ,then use it; /engag
12、e PLL to system;/pllclock=2*osc*(l+SYNR)/(l+REFDV)=176MHz;CLKSEL二0X00; PLLCTL_PLLOX=1;SYNR =0xc0 | 0x0b;REFDV二0x80 | 0x01;POSTDIV二0x00;/disengage PLL to system /turn on PLL/pllclock=2*osc*(l+SYNR)/(l+REFDV)二192MHz;/BUS_asm(nop);_asm(nop);while(!(CRGFLG_LOCK=1);CLKSEL_PLLSEL 二1;void SetBusCLK 104M(vo
13、id)CLOCK二96M/when pll is steady ,then use it; /engage PLL to system;asm(nop);/BUS CL0CK=104MCLKSEL=0X00; PLLCTL_PLLOX=1; SYNR =0xc0 | 0x0c: REFDV=0x80 | 0x01; POSTDIV二0x00;asm(nop);/disengage PLL to system /turn on PLL/pllclock=2*osc*(1+SYNR)/(1+REFDV)=208MHz;/disengage PLL to system /turn on PLLwhi
14、l e(!(CRGFLG_LOCK=l); CLKSEL_PLLSEL =1;void SetBusCLK_120M(void) CLKSEL=OXOO;PLLCTL_PLLON=1;SYNR =0xc0 | OxOd;REFDV二0x80 | 0x01;/when pll is steady ,then use it /engage PLL to system;asm(nop);/BUS CL0CK=120MPOSTDIV二0x00;asm(nop);while(! (CRGFLG_LOCK=1);/pllclock=2*osc*(1+SYNR)/(1+REFDV)=240MHz;/when pll is steady , then use it;CLKSEL_PLLSEL =1;/engage PLL to system;
