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1、I2C与SMBus的区别SMBus是一种二线制串行总线，1996年第一版规范开始商用。它大部分基于I2C总线规范。和 I2C一样，SMBus不需增加额外引脚，创建该总线主要是为了增加新的功能特性，但只工作在100KHZ且专门面向智能电池管理应用。它工作在主/从模式：主器件提供时钟，在其发起一次传输时提供一个起始位，在其终止一次传输时提供一个停止位；从器件拥有一个唯一的7或10位从器件地址。 SMBus与I2C总线之间在时序特性上存在一些差别。首先，SMBus需要一定数据保持时间，而 I2C总线则是从内部延长数据保持时间。SMBus具有超时功能，因此当SCL太低而超过35 ms时，从器件将复位正
2、在进行的通信。相反，I2C采用硬件复位。SMBus具有一种警报响应地址(ARA)，因此当从器件产生一个中断时，它不会马上清除中断，而是一直保持到其收到一个由主器件发送的含有其地址的ARA为止。SMBus只工作在从10kHz到最高100KHZ。最低工作频率10kHz是由SMBus超时功能决定的。Comparing the I2C Bus to the SMBusAbstract: The I2C bus and the SMBus are popular 2-wire buses that are essentially compatible with each other. Normally
3、devices, both masters and slaves, are freely interchangeable between both buses. Both buses feature addressable slaves (although specific address allocations can vary between the two). The buses operate at the same speed, up to 100kHz, but the I2C bus has both 400kHz and 2MHz versions. Complete comp
4、atibility between both buses is ensured only below 100kHz. This application note focuses on the significant differences between I2C and SMB. The I2C bus and the SMBus are popular 2-wire buses that are essentially compatible with each other. Normally devices, both masters and slaves, are freely inter
5、changeable between both buses. Both buses feature addressable slaves (although specific address allocations can vary between the two buses). The buses operate at the same speed, up to 100kHz, but the I2C bus has both 400kHz and 2MHz versions. Obviously, complete compatibility between both buses usin
6、g all devices is ensured only below 100kHz.This application note focuses on the significant differences between the two buses. Although it is assumed that the reader has some knowledge of the I2C bus and/or the SMBus, lets first review some protocol basics: Start and Stop events. These are especiall
7、y important in that they are ways of signaling to an interface that it needs to go to an initialized or reset state. Data and Clock must be high to generate Start and Stop. A master cant generate a Start or Stop unless both the Data (SDA for I2C and SMBData for SMBus) and Clock (SCL for I2C and SMBC
8、lk for SMBus) lines are free (not pulled low). This is a consequence of being an open-collector bus. Start and Stop conditions are the only times there will be a transition on the Data line while Clock is high. Data can change state only when Clock is low during a communication. The data on Data mus
9、t always be ready just prior to a high on Clock and be changed only after Clock has gone low (with the exception of Start and Stop). Figure 1. A typical communication, showing the Start and Stop conditions. Timeout and Clock SpeedTimeout and (as a consequence of timeout) minimum clock speed are the
10、most important differences between the I2C bus and the SMBus.I2C Bus = DC (no timeout)SMBus = 10kHz (35mS timeout) Timeout is where a slave device resets its interface whenever Clock goes low for longer than the timeout, typically 35mSec. Use of a timeout also dictates a minimum speed for the clock,
11、 because it can never go static. Thus, the SMBus has a minimum-clock-speed specification. By comparison, the I2C bus can go static indefinitely. In the I2C bus, either a master or a slave can hold the clock low as long as necessary to process data.All of this comes about as a result of how the two b
12、uses deal with slave errors and recovering from those errors. To understand error recovery, consider that there are two states, Start and Stop, which on a properly designed I2C or SMBus slave dictate that the slave interface go to a specific state. In the case of a Start, the interface should initia
13、lize itself and be ready to receive a communication. This should occur regardless of what preceded the Start condition (for example, if the slave was in the middle of a communication in which the master got confused and had to start over). In the case of a Stop, an interface should again initialize
14、itself, but should be expecting a Start prior to any new communication. Both Starts and Stops are the only Data transitions that take place when Clock is high. In order for the transitions on Data to take place, the Data line (and the Clock line) must be free to allow the master to place highs and l
15、ows on the line as it needs.In the I2C bus, if the slave locks up and holds either Clock or Data low, error recovery is impossible. Very few slave devices actually have the ability to hold Clock. As a result, the most common bus error is slave devices that have ended up in a state where Data (the da
16、ta line) is low. In the I2C bus, a master accomplishes error recovery by clocking Clock until Data is high and then issuing a Start followed by a Stop.In contrast to the I2C bus, SMBus slaves are expected to reset their interface whenever Clock is low for longer than the timeout specified in the SMBus specification of 35mS. As such, SMBus masters such as the Intel PIIX4 dont have any error recovery routine built in. In reality, s
