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1、1题：4选1生成8个library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ff isport(ain:in std_logic_vector(3 downto 0); sel:in std_logic_vector(1 downto 0); y:out std_logic );end ;architecture bhv of ff isbegin y=ain(conv_integer(sel);end bhv;library ieee;use ieee.std_logic_1164.all
2、;package newtype istype ary84 is array (7 downto 0,3 downto 0) of std_logic;type ary82 is array (7 downto 0,1 downto 0) of std_logic;End package;library ieee;use ieee.std_logic_1164.all;use work.newtype.all;entity f isport(ain84:in ary84; sel84:in ary82; y84:out std_logic_vector(7 downto 0); count:o
3、ut std_logic);end ;architecture t of f iscomponent ff isport(ain:in std_logic_vector(3 downto 0); sel:in std_logic_vector(1 downto 0); y:out std_logic );end component;signal y841: std_logic_vector(7 downto 0);begin gen1:for n in 0 to 7 generateux: ff port map(ain84(n,3)&ain84(n,2)&ain84(n,1)&ain84(n
4、,0),sel84(n,1)&sel84(n,0),y841(n);end generate;y84=y841;process(y841)variable tmp:std_logic;begintmp:=1;for i in 0 to 7 looptmp:=tmp and y841(i);end loop;count=tmp;end process;end architecture; 2题：5-4状态机library ieee;use ieee.std_logic_1164.all;entity ff isport(clk,res:in std_logic;ina:in std_logic_v
5、ector(0 to 2);outa:out std_logic_vector(3 downto 0);end ff;architecture f1 of ff istype sta is(s0,s1,s2,s3);signal cs,ns:sta;beginreg:process(clk,res) begin if res=1 then cs=s0; elsif clkevent and clk=1 then cs ns=s1; if ina=101 then outa=0010; elsif ina=111 then outa outa=1001; if ina=000 then ns=s
6、1; elsif ina=110 then ns=s2;else ns outa=1111; if ina=011 then ns=s1; elsif ina=100 then ns=s2; else ns ns=s0; if ina=101 then outa=1101; elsif ina=011 then outa=1110; end if; end case; end process; end architecture;3题：例题5-2library ieee;use ieee.std_logic_1164.all;entity ff isport(clk,res:in std_log
7、ic;ina:in std_logic_vector(0 to 2);outa:out std_logic_vector(3 downto 0);end ff;architecture f1 of ff istype sta is(s0,s1,s2,s3);signal cs,ns:sta;beginreg:process(clk,res) begin if res=1 then cs=s0; elsif clkevent and clk=1 then cs ns=s1; if ina=101 then outa=0010; elsif ina=111 then outa outa=1001;
8、 if ina=000 then ns=s1; elsif ina=110 then ns=s2;else ns outa=1111; if ina=011 then ns=s1; elsif ina=100 then ns=s2; else ns ns=s0; if ina=101 then outa=1101; elsif ina=011 then outa=1110; end if; end case; end process; end architecture;4题library ieee;use ieee.std_logic_1164.all;entity ff isport(clk
9、:in std_logic; q1,q2:out std_logic);end entity;architecture f1 of ff isprocedure dd (signal clk1:in std_logic;- signal q:inout std_logic) is begin if clk1event and clk1=1 then q=not q;end if; return ; end dd;signal qs1,qs2:std_logic;beginprocess(clk)begindd(clk,qs1);dd(qs1,qs2);end process;q1=qs1;q2
10、 cin cin cin cin cin cin cin cin cin cin cin=1111111;END CASE;END PROCESS;END ARCHITECTURE;7题例题7-4奇偶校验位LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ff IS PORT(a:in STD_LOGIC_VECTOR(7 DOWNTO 0); y:OUT STD_LOGIC);END ENTITY;ARCHITECTURE f OF ff ISBEGINPROCESS(a)variable tmp:STD_LOGIC:=0;BEGINfor n in 0 to 7 looptmp:=tmp xor a(n);end loop;y=tmp;END PROCESS;END ARCHITECTURE;8题4-2编码器library ieee;use ieee.std_logic_1164.all;entity ff isport(ain:in std_logic_vector(0 to 3); cin:out std_logic_vector(0 to 1);end entity;architecture f of ff isbegin
