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1、1. Shown below are buffer-chain designs. (1) Calculate the minimum delay of a chain of inverters for the overall effective fan-out of 64/1. (2) Using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply, design a circuit simulation scheme to verify them with their correspondent para
2、meters of N, f, and tp.(1)所以最佳反相器数目约为3通过仿真可以得到tphl=1.3568E-11 tplh=1.7498E-11 tp0=1.5533E-11(2)N=1时，tphl= 5.2735E-10 tplh= 8.1605E-10 tpd= 6.7170E-10N=2时，tplh=2.2478E-10 tphl=2.5567E-10 tpd=2.4023E-10N=3时，tphl=2.0574E-10 tplh=2.1781E-10 tpd=2.1178E-10N=4时，tplh=2.1579E-10 tphl=2.2189E-10 tpd=2.1884E-
3、10从仿真结果可以看出N=3或者N=4时延迟时间最优，且N=2、3、4得到的仿真延迟时间与理论推导的时间比较接近，比例基本上是18、15、15.3，而N=1时仿真得到的延迟时间远小于理论推导的时间，但是最优结果依旧是N=3,f=4,tp=15。* SPICE INPUT FILE: Bsim3demo1.sp-a chain of inverters.param Supply=1.8.libC:synopsysHspice_A-2007.09tsmc018mm018.l TT.option captab.option list node post measout.tran 10p 6000p*
4、.param tdval=10p.meas tran tplh trig v(in) val=0.9 td=tdval rise=2+targ v(out) val=0.9 rise=2.meas tran tphl trig v(in) val=0.9 td=tdval fall=2+targ v(out) val=0.9 fall=2.meas tpd param=(tphl+tplh)/2*macro definitions*nmos1*.subckt nmos1 n1 n2 n3mn n1 n2 n3 Gnd nch l=0.2u w=0.4u ad=0.2p2 pd=0.4u as=
5、0.2p2 ps=0.4u.ends nmos1*pmos1*.subckt pmos1 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=0.8u ad=0.4p2 pd=0.8u as=0.4p2 ps=0.8u.ends pmos1*.subckt inv1 in outxmn out in Gnd nmos1xmp out in Vcc pmos1vcc Vcc Gnd Supply.ends inv1*nmos2*.subckt nmos2 n1 n2 n3mn n1 n2 n3 Gnd nch l=0.2u w=1.12u ad=0.56p2 pd=1.12
6、u as=0.56p2 ps=1.12u.ends nmos2*pmos2*.subckt pmos2 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=2.24u ad=1.12p2 pd=2.24u as=1.12p2 ps=2.24u.ends pmos2*.subckt inv2 in outxmn out in Gnd nmos2xmp out in Vcc pmos2vcc Vcc Gnd Supply.ends inv2*nmos3*.subckt nmos3 n1 n2 n3mn n1 n2 n3 Gnd nch l=0.2u w=3.2u ad=1.6
7、p2 pd=3.2u as=1.6p2 ps=3.2u.ends nmos3*pmos3*.subckt pmos3 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=6.4u ad=3.2p2 pd=6.4u as=3.2p2 ps=6.4u.ends pmos3*.subckt inv3 in outxmn out in Gnd nmos3xmp out in Vcc pmos3vcc Vcc Gnd Supply.ends inv3*nmos4*.subckt nmos4 n1 n2 n3mn n1 n2 n3 Gnd nch l=0.2u w=9.04u ad=
8、4.52p2 pd=9.04u as=4.52p2 ps=9.04u.ends nmos4*pmos4*.subckt pmos4 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=18.08u ad=9.04p2 pd=18.08u as=9.04p2 ps=18.08u.ends pmos4*.subckt inv4 in outxmn out in Gnd nmos4xmp out in Vcc pmos4vcc Vcc Gnd Supply.ends inv4*main circuit netlistxinv1 in out1 inv1xinv2 out1 ou
9、t2 inv2xinv3 out2 out3 inv3xinv4 out3 out inv4cl out Gnd 154.24fVin in Gnd 0.9 pulse(0.0 1.8 219p 40p 40p 1100p 2400p).print tran v(in) v(out).end2. Consider the logic network below, which may represent the critical path of a more complex logic block. The output of the。 network is loaded with a capa
10、citance which is 5 times larger than the input capacitance of the first gate, which is a minimum-sized inverter. The effective fanout of the path hence equals F = CL/Cg1 = 5. Using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply, design a circuit simulation scheme to verify (1)
11、 the OPTIMAZATIOM parameters of g, f, and s for each of the inverter and gates and The path logical effort The total path effort The optimal gate effort 在所有的nmos和pmos均采用最小尺寸晶体管的情况下tplh=1.9047E-10 tphl=2.2742E-10 tpd=2.0895E-10在所有所有的mos管尺寸均是前一个mos管尺寸的2倍的情况下tplh=1.8353E-10 tphl=2.4356E-10 tpd=2.1355E-
12、10在参数最优的情况下tplh= 1.7151E-10 tphl=2.2853E-10 tpd=2.0002E-10所以最优参数为上面的推到过程。* SPICE INPUT FILE: Bsim3demo1.sp-a chain of inverters.param Supply=1.8.libC:synopsysHspice_A-2007.09tsmc018mm018.l TT.option captab.option list node post measout.tran 10p 6000p*.param tdval=10p.meas tran tplh trig v(in) val=0.
13、9 td=tdval rise=2+targ v(out) val=0.9 rise=2.meas tran tphl trig v(in) val=0.9 td=tdval fall=2+targ v(out) val=0.9 fall=2.meas tpd param=(tphl+tplh)/2*macro definitions*nmos1*.subckt nmos1 n1 n2 n3mn n1 n2 n3 Gnd nch l=0.2u w=0.4u ad=0.2p2 pd=0.4u as=0.2p2 ps=0.4u.ends nmos1*pmos1*.subckt pmos1 p1 p
14、2 p3mp p1 p2 p3 Vcc pch l=0.2u w=0.8u ad=0.4p2 pd=0.8u as=0.4p2 ps=0.8u.ends pmos1*.subckt inv1 in outxmn out in Gnd nmos1xmp out in Vcc pmos1vcc Vcc Gnd Supply.ends inv1*nmos2*.subckt nmos2 n1 n2 n3 n4mn n1 n2 n3 n4 nch l=0.2u w=0.772u ad=0.386p2 pd=0.772u as=0.386p2 ps=0.772u.ends nmos2*pmos2*.subckt pmos2 p1 p2 p3 p4mp p1 p2 p3 p4 pch l=0.2u w=1.544u ad=0.772p2 pd=1.544u as=0.772p2 ps=1.544u.ends pmos2*.subckt nand in1 in2 in3 outxmn1 d1
