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1、半加器源程序:module wu077(a,b,cin,s,cont); input a,b,cin;output s,cont;reg1:0 out;assign s=out1:1;assign cont=out1:0; always(a or b or cin) begincase(a,b,cin)3b000: out=2b00;3b001: out=2b10;3b010: out=2b10;3b011: out=2b01;3b100: out=2b10;3b101: out=2b01;3b110: out=2b01;3b111: out=2b11;default: out=2bx;end
2、caseendendmodule测试程序timescale lns/lns module wu077t;reg ina,inb,incin;wire s,co;initialbeginforeverbegin#100 ina=0;inb=0;incin=0;#100 ina=0;inb=0;incin=1;#100 ina=0;inb=1;incin=0;#100 ina=0;inb=1;incin=1;#100 ina=1;inb=0;incin=0;#100 ina=1;inb=0;incin=1;#100 ina=1;inb=1;incin=0;#100 ina=1;inb=1;inci
3、n=1;endendwu077 m(.a(ina),.b(inb),.s(s),.cont(co),.cin(incin); endmodule全加器源程序:module wu077(a,b,cin,s,cont); input a,b,cin;output s,cont;reg1:0 out;assign s=out1:1;assign cont=out1:0; always(a or b or cin) begincase(a,b,cin)3b000: out=2b00;3b001: out=2b10;3b010: out=2b10;3b011: out=2b01;3b100: out=2
4、b10;3b101: out=2b01;3b110: out=2b01;3b111: out=2b11;default: out=2bx; endcase end endmodule测试程序:timescale lns/lnsmodule wu077t;reg ina,inb,incin;wire s,co;initialbeginforeverbegin#100 ina=0;inb=0;incin=0;#100 ina=0;inb=0;incin=1;#100 ina=0;inb=1;incin=0;#100 ina=0;inb=1;incin=1;#100 ina=1;inb=0;inci
5、n=0;#100 ina=1;inb=0;incin=1;#100 ina=1;inb=1;incin=0;#100 ina=1;inb=1;incin=1;endendwu077 m(.a(ina),.b(inb),.s(s),.cont(co),.cin(incin); endmodule比较器源程序:module wu077(gg,ss,ee,data,b);input data,b;output gg,ss,ee;reg gg,ss,ee;always(data or b)begin if(datab) begingg=1;ss=0;ee=0;endelse if(datab)begin gg=0;ss=1;ee=0;endelsebegingg=0;ss=0;ee=1;endendendmodule测试程序:in elude wu077.vmodule wu077t;reg data,b;wire gg,ss,ee;initialbeginforeverbegin#100 data=0;b=0;#100 data=0;b=1;#100 data=1;b=0;#100 data=1;b=1;endendwu077 m(.data(data),.b(b),.gg(gg),.ee(ee),.ss(ss);endmodule