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1、7.5 英文资料及中文翻译Generating a Serial SignalAlthough a parallel input-output scheme can provide fast data transfer and is simple in operation, it has the disadvantage of requiring a large number of interconnections. As an example typical 8 bit parallel data port uses 8 data lines, plus one or two handsha
2、ke lines and one or more ground return lines. It is fairly common practice to provide a separate ground return line for each signal line, so an 8 bit port could typically use a 20 core interconnection cable. Whilst such a multiway cable is quite acceptable for short distance links, up to perhaps a f
3、ew meters, it becomes too expensive for long distance links where, in addition to the cost of the multiword cable, separate driver and receiver circuits may be required on each of the 10 signal lines. Where part of the link is to be made via a radio link, perhaps through a space satellite, separate
4、radio frequency channels would be required for each data bit and this becomes unacceptable.An alternative to the parallel transfer of data is a serial in which the states of the individual data bits are transmitted in sequence over a single wire link. Each bit is allocated a fixed time slot. At the
5、receiving end the individual bit states are detected and stored in separate flip-flop stages, so that the data may be reassembled to produce a parallel data word. The advantage of this serial method of transmission is that it requires only one signal wire and a ground return, irrespective of the num
6、ber of bits in the data word being transmitted. The main disadvantage is that the rate at which data can be transferred is reduced in comparison with a parallel data transfer, since the bits are dealt with in sequence and the larger the number of bits in the word, the slower the maximum transfer spe
7、ed becomes. For most applications however, a serial data stream can provide a perfectly adequate data transfer rate . This type of communication system is well suited for radio or telephone line links, since only one communication channel is required to carry the data.We have seen that in the CPU sy
8、stem data is normally transferred in parallel across the main data bus, so if the input -output data is to be in serial form, then a parallel to serial data conversion process is required between the CPU data bus and the external I/O line. The conversion from parallel data to the serial form could b
9、e achieved by simply using a multiplexed switch, which selects each data bit in turn and connects it to the output line for a fixed time period. A more practical technique makes use of a shift register to convert the parallel data into serial form.A shift register consists of a series of D type flip
10、-flops connected in a chain, with the Q output of one flip-flop driving the D input of the next in the chain. All of the flip-flops ate clocked simultaneously by a common clock pulse, when the clock pulse occurs the data stored in each flip-flop is transferred to the next flip-flop to the right in t
11、he chain. Thus for each clock pulse the data word is effectively stepped along the shift register by one stage, At the end of the chain the state of the output flip-flop will sequence through the states of the data bits originally stored in the register. The result is a serial stream of data pulses
12、from the end of the shift register.In a typical parallel to serial conversion arrangement the flip-flops making up the shift register have their D input switchable. Initially the D inputs are set up in a way so that data can be transferred in parallel from the CPU data bus into the register stages.
13、Once the data word has been loaded into the register the D inputs are switched so that the flip-flops from a shift register .Now for each successive clock pulse the data pattern is shifted through the register and comes out in serial form at the right hand end of the register. At the receiving end t
14、he serial data will usually have to be converted back into the parallel form before it can be used. The serial to parallel conversion process can also be achieved by using a shift register .In this case the serial signal is applied to the D input of the stage at the left hand end of the register. As
15、 each serial bit is clocked into the register the data word again moves step by step to the right, and after the last bit has been shifted in the complete data word will be assembled within the register .At this point the parallel data may be retrieved by simply reading out the data from individual
16、register stages in parallel It is important that the number of stages in the shift register should match the number of bits in the data word, if the data is to be properly converted into parallel form.To achieve proper operation of the receiving end of a serial data link, it is important that the clock pulse is applied to the receive shift register at a time when the data level on the serial line is stable. It is possible to have the clock generated at either end of the link, but
