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1、Antifuse FPGA FamiliesAxcelerator, SX-A, eX, MXnctelPOWER MATTERSAxcelerator FPGA Family亠 High-Performance, Sea-of-Modules architecture 500+ MHz internal performance 350+ MHz system performance Technology 0.15p, 7 Layer Metal (all Al) CMOS Amorphous M2M Antifuse Density: from 1 25K to 2M system gate
2、s Maximum 21,504 Registers Architecture Optimized for Performance Fully fracturable logic cluster with High Logic Module utilization Embedded RAM blocks with integrated FIFO control logic at 500+ MHz performance Improved High Fanout Performance, Tree55 buffering of high-fanout nets Superior Clock ma
3、nagement Easy-to-use global clocks Flexible clocking schemes 1 GHz PLLs No “clock floorplanning requiredSX-A FPGA FamilynctelPOWER MATTERS Perform ance 250 MHz system performance 350 MHz internal performance Technology Density: from 1 2,000 to 1 05000 system gates Antifuse-based FPGA on 0.22pm/0.25p
4、m process, 2.5V Core Maximum 4,024 flip-flops Versatility and flexibility for system integration Full support of 3.3V & 5V PCI Hot-swapping Mixed-voltage I/Os (2.5V, 3.3V, 5V)eX FPGA FamilynctelPOWER MATTERS Performance 240 MHz system performance 350 MHz internal performance 3.9ns clock-to-out (pad-
5、to-pad) Technology Antifuse-based FPGA on 0.22pm process, 2.5V core Density: from 3,000 to 1 2,000 system gates Equivalent to CPLDs from 64 to 256 macrocells Versatility and flexibility for system integration Mixed-voltage support 2.5V, 3.3V, 5V I/O drive and 5V tolerant I/Os Hot-swapping Availabili
6、ty in chip-scale (0.8mm) BGA packageSingle-chip and nonvolatileAntifuse Product PresentationMay 08#Where Do They Fit?nctelPOWER MATTERSMarketsFullFeaturedFPGAAntifuse Product PresentationMay 08#ProASIC3 and IGLOO350MHzEconomyFPGAProASIC 迤150MHzS)GACPLDEquivalent250 MHzIIIII3,00010300010050001M 2MDen
7、sity (Gates)Antifuse Product PresentationMay 08#MX FPGA Family -5VnctelPOWER MATTERSAntifuse Product PresentationMay 08#Antifuse Product PresentationMay 08#IndustryJs leading price/performance FPGA solution at 5V Single-chip solution Low power consumption Superior performance Robust design security
8、Low cost logic integration 100% device utilization and 100% pin-locking Multiplex l/Os3 with 5.0V and 3.3V I/O support and PCI compliance Re-spinning Legacy 5V Designs No expensive NRE charges No minimum quantities Short prototyping cycles and quick time-to-market Fast, easy response to implement la
9、st-minute design changes Design to meet or exceed current performanceFlexibility of not having to migrate down the voltage pathAntifuse Product PresentationMay 08#Design SecuritynctelPOWER MATTERSAntifuse Product PresentationMay 08#Antifuse Product PresentationMay 08#Bitstream can be captured Device
10、 is easily cloned Encryption can be compromised Your IP is lostUnprogrammed Fuse SRAM FPGAs have security holesProgrammed Fuse Antifuse FPGAs have no security holes No bitstream download at power up Programming info cannot be read out of the device Whether security fuse is programmed or not Programm
11、ed state of fuse can only be detected in cross-section Needle in a haystack problemFuseLock FuseLock Security fuses prevent invasive attackFirm Error Immunity Radiation effects are not confined to spacecraft. Ground level and airborne applications are affected by radiation too!SRAM FPGAAntifus FPGAF
12、lash FPGALoss of ConfigurationYesNoNoSystem Critical FailureData Upsets inFlip-FlopsYesYesYesThese Effects are Easily Mitigated and Affect All lech nologies.Data Upsets in MemoryYesYesYesData Upsets in Combinatorial LogicYesYesYesnctelPOWER MATTERSThe effects of radiation can be devastating in SRAM
13、FPGAs and the applications they host.Antifuse Product PresentationMay 08#Antifuse Product PresentationMay 08#Antifuse Product PresentationMay 08#Heavy Ions from Neutron Impact cause Trail of Ionization and Current PulseAlpha radiation causes a trail of ionization and resulting current pulseAntifuse
14、Product PresentationMay 08#Antifuse Product PresentationMay 08#Firm Error Immunity、SRAM-FPGA Soft vs Firm ErrorsnctelPOWER MATTERSAntifuse Product PresentationMay 08#Firm Error Immunity、SRAM-FPGA Soft vs Firm ErrorsAntifuse Product PresentationMay 08#Firm Error Immunity、SRAM-FPGA Soft vs Firm ErrorsNeutron or Alpha- induced soft error causes transie nt data corruption in block RAM.Can be corrected with EDAC.Neutron or Alpha induced firm error causes configuration c
