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1、180C H A PT ER5THE CMOS INVERTERQuantification of integrity, performance, and energy metrics of an inverterOptimization of an inverter design5.1Exercises and Design Problems5.2The Static CMOS Inverter An IntuitivePerspective5.3Evaluating the Robustness of the CMOSInverter: The Static Behavior5.3.1Sw
2、itching Threshold5.3.2Noise Margins5.3.3Robustness Revisited5.4Performance of CMOS Inverter: The DynamicBehavior5.4.1Computing the Capacitances5.4.2Propagation Delay: First-OrderAnalysis5.4.3Propagation Delay from a DesignPerspective5.5Power, Energy, and Energy-Delay5.5.1Dynamic Power Consumption5.5
3、.2Static Consumption5.5.3Putting It All Together5.5.4Analyzing Power Consumption UsingSPICE5.6Perspective: Technology Scaling and itsImpact on the Inverter MetricsSection 5.1Exercises and Design Problems1815.1Exercises and Design Problems1.M, SPICE, 3.3.2 The layout of a static CMOS inverter is give
4、n in Figure 5.1. ( = 0.125m).a. Determine the sizes of the NMOS and PMOS transistors.SolutionThe sizes are wn=1.0m, ln=0.25m, wp=0.5m, and lp=0.25 m.b. Plot the VTC (using HSPICE) and derive its parameters (VOH, VOL, VM, VIH, and VIL).SolutionThe inverter VTC is shown below. For a static CMOS invert
5、er with a supply voltage of2.5 V, VOH=2.5 V and VOL=0 V. In order to calculate Vm, note from the VTC that the value isbetween 0.8 V and 0.9 V. Therefore, the NMOS is saturated and the PMOS is velocity satu-rated. Let Vin=Vout=Vmand set the currents equal to obtain the following equation:(kn/2)(VGS-V
6、TN)2(1+VDS)=kpVDSAT(VGS-VTP)-(VDSAT/2)(1+VDS)Substitute the appropriate values and solve numerically to find Vm=0.883 V.Use the VTC data to solve for VILand VIHnumerically. The result is that VIH=0.97 V andVIL=0.56 V.c. Is the VTC affected when the output of the gates is connected to the inputs of 4
7、 similargates?SolutionNo. CMOS gates are a purely capacitive load so the DC circuit characteristics are notaffected.00.511.522.50.500.511.522.53Input Voltage (V)Output Voltage (V)VILVIHVM182THE CMOS INVERTERChapter 5d. Resize the inverter to achieve a switching threshold of approximately 0.75 V. Do
8、not lay-out the new inverter, use HSPICE for your simulations. How are the noise marginsaffected by this modification?SolutionChanging the NMOS sizing to wn=2.0m moves the switching threshold to 0.75 V.This increases NMHand decreases NML.2.Figure 5.2 shows a piecewise linear approximation for the VT
9、C. The transition region isapproximated by a straight line with a slope equal to the inverter gain at VM. The intersectionof this line with the VOHand the VOLlines defines VIHand VIL.a. The noise margins of a CMOS inverter are highly dependent on the sizing ratio, r = kp/kn,of the NMOS and PMOS tran
10、sistors. Use HSPICE with VTn= |VTp| to determine the valueof r that results in equal noise margins? Give a qualitative explanation.SolutionThe TSMC 0.25m models were used for simulation and the threshold voltages ofNMOS and PMOS devices are nearly equal in this process. A value near r=1 should resul
11、t inequal noise margins, since the transistors will be closely matched. HSPICE showed that theresulting noise margins for this sizing were NMH=0.97 V and NML=1.1 V. The mismatch isdue to the fact that the PMOS threshold voltage is actually slightly lower, so the PMOS isstronger and the upper noise m
12、argin is reduced. The actual value that results in equal noisemargins is r=0.83.b. Section 5.3.2 of the text uses this piecewise linear approximation to derive simplifiedexpressions for NMHand NMLin terms of the inverter gain. The derivation of the gain isbased on the assumption that both the NMOS a
13、nd the PMOS devices are velocity saturatedat VM. For what range of r is this assumption valid? What is the resulting range of VM?SolutionFigure 5.1CMOS inverter layout.InOutGNDVDD= 2.5 V.PolyMetal1NMOSPMOSPolyMetal12Section 5.1Exercises and Design Problems183Using the equations for finding the regio
14、n of operation, it can be shown that the PMOSand NMOS are both velocity saturated only while the switching threshold is between 1.06 Vand 1.10 V. Since this range may be considered inclusive, we can assume that both devices arevelocity saturated and set the currents equal with VIN=VOUT=VMto find kp/
15、kn. The result isthat kp/knmust be between 0.34 and 0.41. This result can be checked by sizing the devicesaccordingly and testing the resulting VMin HSPICE. The result gives a range of 1.04 V to1.09 V. This makes sense, because the NMOS must be much stronger than the PMOS toachieve a switching thres
16、hold near 1 V.c. Derive expressions for the inverter gain at VMfor the cases when the sizing ratio is justabove and just below the limits of the range where both devices are velocity saturated.What are the operating regions of the NMOS and the PMOS for each case? Consider theeffect of channel-length modulation by using the following expression for the small-signalresistance in the saturation region: ro,sat= 1/(ID).Solution:When VMis slightly larger than 1.1 V, the NMOS is velocity saturated and
