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1、锁相环技术中英文翻译外文资料 Phase-locked loop Technology :A phase-locked loop or phase lock loop PLL is a control system that generates a signal that has a fixed relation to the phase of a reference” signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatica
2、lly raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. A phase-locked loop is an example of a control system using negative feedback. Tn the order of the PLL is the way of made the frequency stability in the send up wireless
3、, include VCO and PLL integrated circuits, VCO send up a signal, some of the signal is output, and the other through the frequency division with PLL integrated circuits generate the local signal making compared. In the order to remain the same, it s must be remain the phase displacement same. Tf the
4、 phase displacement have some changes, the output of the PLL integrated circuits have some changes too, to controlle VCO until phase difference to restore, make both cotrolled oscillator s frequency and phase with input signal which is close-loop electronic circuit keep firm relationship.Phase-locke
5、d loops are widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrated
6、circuit can provide a compete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a cycle per second up to many gigahertz.Earliest research towards what became known as the phase-locked loop goes back to 1932, when B
7、ritish researchers developed an alternative to Edwin Armstrong s superheterodyne receiver, the Homodyne. In the homodyne or synchrodyne system, a local oscillator was tuned to the desired input frequency and multiplied with the input signal. The resulting output signal included the original audio mo
8、dulation information. The intent was to develop an alternative receiver circuit that required fewer tuned circuits than the superheterodyne receiver. Since the local oscillator would rapidly drift in frequency, an automatic correction signal was appl ied to the oscillator, maintaining it in the same
9、 phase and frequency as the desired signal. The technique was described in 1932, in a paper by H.de Bellescise, in the French journal Onde Electrique.In analog television receivers since at least the late 1930s, phase-locked-loop horizontal and vertical sweep circuits are locked to synchronization p
10、ul ses in the broadcast signal. When Signetics introduced a line of monolithic integrated circuits that were complete phase-locked loop systems on a chip in 1969, applications for the technique multiplied.A few years later RCA introduced the CD4046 CMOS Micropower Phase-Locked Loop, which became a p
11、opular integrated circuit.Applications：Phase-locked loops are widely used for synchronization purposes; in space communications for coherent carrier trackng and threshold extension, bit synchronization, and symbol synchronization. Phase-locked loops can also be used to demodulate frequency-modulated
12、 signals. In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple of a reference frequency, with the same stability as the reference frequency.Clock recovery :Some data streams, especially high-speed serial data streams such as the raw stream of data from the magnetic
13、 head of a disk drive , are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a PLL. This process is referred to as clock recovery. In order for this scheme to work, the data st
14、ream must have a transition frequently enough to correct any drift in the PLLs oscillator. Typically, some sort of redundant encoding is used; 8B10B is very common.Deskewing :If a clock is sent in parallel with data, that clock can be used to sample the data. Because the clock must be received and a
15、mplified before it can drive the fl ip-flops which sample the data, there will be a finite, and process-, temperature-, and voltage-dependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating this del
16、ay is to include a deskew PLL on the receive side, so that the clock at each data flip-flop is phase-matched to the received clock. In that type of application, a special form of a PLL called a Delay-Locked Loop DLL is frequently used.Clock generation：Many electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-freq
