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1、 SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER DATASHEET Rev. 1.3 26 July 2005 Track ID: JATR-1076-21 RTL8201BL RTL8201BL-LF RTL8201BL Datasheet Single Chip Single Port 10/100M Fast Ethernet Phyceiver ii Track ID: JATR-1076-21 Rev. 1.3 COPYRIGHT 2005 Realtek Semiconductor Corp. All rights
2、reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty
3、of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADE
4、MARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineers general information on the Realtek RTL8201B
5、L chip. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development
6、 process. REVISION HISTORY Revision Release Date Summary 1.1 2002/02/01 Power Dissipation: Remove 2.5V power consumption 100Mbps Network Interface: R5 is changed from 5.6K to 5.9K Reset, and Transmit Bias(RTSET): R5 is changed from 5.6K to 5.9K Schematic Layout: R5 is changed from 5.6K to 5.9K 1.2 2
7、002/03/29 Reset and other pins: Add pin description for pin 32 and pin 8 Power and Ground pins: Remove pin description of pin 32 and pin 8 3.3V power supply and voltage conversion circuit: Add description: “Strongly emphasize here, could not provide external 2.5V produced by any other power device f
8、or PWFBOUT and PWFBIN”. Schematic Layout: 1. Modify net label: Pin32: AVDD25 - PWFBOUT Pin8: DVDD25- PWFBIN 2. Add pull-high resistor for MDIO 3. Modify ResetB circuit to meet wake-on-LAN application 1.3 2005/07/26 Cosmetic layout changes RTL8201BL Datasheet Single Chip Single Port 10/100M Fast Ethe
9、rnet Phyceiver iii Track ID: JATR-1076-21 Rev. 1.3 Table of Contents 1. INTRODUCTION .1 2. SYSTEM APPLICATIONS1 3. FEATURES2 4. BLOCK DIAGRAM3 5. PIN ASSIGNMENTS 4 5.1. LEAD (PB)-FREE PACKAGE AND VERSION IDENTIFICATION.4 6. PIN DESCRIPTION5 6.1. 100MBPS MII the signal is deasserted at the end of the
10、 packet. The signal is valid on the rising of the RXC. RXD3:0 O 18, 19, 20, 21 Receive Data: These are the four parallel receive data lines aligned on the nibble boundaries driven synchronously to the RXC for reception by the external physical unit (PHY). RXER/ FXEN O/LI 24 Receive error: if any 5B
11、decode error occurs, such as invalid J/K, T/R, invalid symbol, this pin will go high. Fiber/UTP Enable: During power on reset, this pin status is latched to determine at which media mode to operate: 1: Fiber mode 0: UTP mode An internal weak pull low resistor, sets this to the default of UTP mode. I
12、t is possible to use an external 5.1K pull high resistor to enable fiber mode. After power on, the pin operates as the Receive Error pin. MDC I 25 Management Data Clock: This pin provides a clock synchronous to MDIO, which may be asynchronous to the transmit TXC and receive RXC clocks. The clock rat
13、e can be up to 2.5MHz. MDIO I/O 26 Management Data Input/Output: This pin provides the bi-directional signal used to transfer management information. 6.2. SNI (Serial Network Interface): 10Mbps only Symbol Type Pin No. Description COL O 1 Collision Detect RXD0 O 21 Received Serial Data CRS O 23 Carr
14、ier Sense RXC O 16 Receive Clock: Resolved from received data TXD0 I 6 Transmit Serial Data TXC O 7 Transmit Clock: Generate by PHY TXEN I 2 Transmit Enable: For MAC to indicate transmit operation RTL8201BL Datasheet Single Chip Single Port 10/100M Fast Ethernet Phyceiver 6 Track ID: JATR-1076-21 Re
15、v. 1.3 6.3. Clock Interface Symbol Type Pin No. Description X2 O 47 25MHz Crystal Output: This pin provides the 25MHz crystal output. It must be left open when X1 is driven with an external 25MHz oscillator. X1 I 46 25MHz Crystal Input: This pin provides the 25MHz crystal input. If a 25MHz oscillato
16、r is used, connect X1 to the oscillators output. Refer to section 8.3 to obtain clock source specifications. 6.4. 100Mbps Network Interface Symbol Type Pin No. Description TPTX+ TPTX- O O 34 33 Transmit Output: Differential pair shared by 100Base-TX, 100Base-FX and 10Base-T modes. When configured as 100Base-TX, output is an MLT-3 encoded waveform. When configured as 100Base-FX, the output is pseudo-ECL level. RTSET I 28 Transmit Bias Resistor Connection: This pin should be pulled to G
