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1、Content IC DESIGN MAGAZINE VOLUME 35www.C 1Mar. 2003 Design-for-TestabilityDFT 8-bit RISCCIC DFT Free IPhttp:/www.free- DFT Reprint Copyright 2001 by Chip123 Technology Co., Ltd. All rights reserved ISSN 1609-8633 Reprint Copyright 2001 by Chip123 Technology Co., Ltd. All rights reserved ISSN 1
2、609-8633 IC DESIGN MAGAZINE VOLUME 35 www.C 2Mar. 2003 DFT Free-RISC 8DFT Free-RISC 88-bitMicrochip 16C57 Verilog ALU Instruction DecoderRegister FileCPU Register FileFlip-Flop Memory BIST (Built In Self Test) Memory Compiler two-port asynchronous SRAM Register File Memory Compilersynchronous ROMROM
3、 sample2048x12ROM72x8 SRAMDFT Memory BISTMemory BIST embedded SRAMROM full-scanscan chain ATPGAutomatic Test Pattern Generation SynTestMemory BIST SynTestSRAMBISTMemory BIST .mdfmemory description file BIST.mdfsrambist memory.mdf Memory BISTRTL codesynthesis scriptsimulation testbench report 1) Asyn
4、chronous Two-port SRAM Specification (c4mtram72x8) Memory Attributes: Word depth: 72 Address width: 7 Word width: 8 Small address: 7b0000000 Maximum address 7b1000111 Number of ports: two Memory Port Attributes: Port 1 Port type: Read Address signal: RA Reprint Copyright 2001 by Chip123 Technology C
5、o., Ltd. All rights reserved ISSN 1609-8633 IC DESIGN MAGAZINE VOLUME 35www.C 3Mar. 2003 Data out signal: DO Read enable signal: REB, active low Output enable signal: OEB, active low Port 2 Port type: Write Address signal: WA Data in signal: DI Write enable signal: WEB BIST Constraint Synchronous
6、reset: True Clock cycle: 20ns Time scale: 1ns/10ps c4mtram72x8.mdf %GLOBAL %TIMESCALE1ns/10ps; %SYNC_RESETTRUE; %CLK_CYCLE20; %BIST_CLK_TRIGGER posedge; %MEMORY c4mtram72x8 %TIMESCALE1ns/10ps; %TYPESRAM; %DATA_BITS8; %ADDR_BITS7; %LOW_ADDR7b0000000; %HIGH_ADDR7b1000111; %LATENCY0; %PORT R %TYPE r; %
7、ADDRESS RA ; %DATA_OUT DO ; %READ_EN -REB; Reprint Copyright 2001 by Chip123 Technology Co., Ltd. All rights reserved ISSN 1609-8633 IC DESIGN MAGAZINE VOLUME 35 www.C 4Mar. 2003 DFT %OUTPUT_EN -OEB; %PORT W %TYPEw; %ADDRESSWA ; %DATA_INDI ; %WRITE_EN-WEB; GLOBALVerilogtimescaleBIST resetBISTclock
8、MEMORY timescaleSRAM or ROM 72word7 b00000007b1000111BIST BISTlatency latencyclock latency0port portport -.mdfsrambist c4mtram72x8 = SYNTEST SRAMBIST REPORT FILE = TOOL : srambist V1.1.0 r01 (08/15/00 16:30:26) TIME : Wed Mar 15 08:28:26 2002 OPTIONS SELECTED : -algorithm MOIV NUMBER OF MEMORIES : 1
9、 THE CLOCK BEING USED AS THE BIST CLOCK: All memories are asynchronous. Please supply a test clock and link it to the Tclk port of the top module. BIST CLOCK TRIGGERING : Reprint Copyright 2001 by Chip123 Technology Co., Ltd. All rights reserved ISSN 1609-8633 IC DESIGN MAGAZINE VOLUME 35www.C 5Ma
10、r. 2003 Positive triggered clock. TOTAL BIST CYCLES : 1877 FILES GENERATED : c4mtram72x8_top.v : Top module BIST connection file c4mtram72x8_wrapper.v : RAM wrapper file c4mtram72x8_rb.v : BIST RTL file c4mtram72x8_sim.v : BIST simulation testbench file c4mtram72x8.scp : Synopsys synthesis script fi
11、le c4mtram72x8.bist.rpt : Report file = END SRAMBIST REPORT FILE = March 13N Moving Inversion Algorithmfault model March ElementsBIST Configuration File.BCF.BCFBIST BISTclockBIST TclkBISTclock clockBISTclock RLT 2) Synchronous ROM Specification (c4msrom0101) Memory Attributes: Word depth: 2048 Addre
12、ss width: 11 Word width: 12 Small address: 11b00000000000 Maximum address 11b11111111111 Number of ports: single port Memory Port Attributes: Port type: Read Address signal: A Data out signal: O Clock signal : CLK with positive edge trigger Output enable signal: OE, active high Reprint Copyright 200
13、1 by Chip123 Technology Co., Ltd. All rights reserved ISSN 1609-8633 IC DESIGN MAGAZINE VOLUME 35 www.C 6Mar. 2003 DFT BIST Constraint Synchronous reset: True Clock cycle: 20ns Time scale: 1ns/10ps Rom content file: romdata c4msrom0101.mdf %GLOBAL %TIMESCALE1ns/10ps; %SYNC_RESETTRUE; %CLK_CYCLE20;
14、 %BIST_CLK_TRIGGER posedge; %MEMORY c4msrom0101 %TIMESCALE1ns/10ps; %TYPEROM; %DATA_BITS12; %ADDR_BITS11; %LOW_ADDR11b00000000000; %HIGH_ADDR11b11111111111; %CLOCKCLK; %LATENCY0; %ROM_CONTENT_FILE romdata; %PORT R %TYPEr; %ADDRESSA; %DATA_OUTO; %OUTPUT_EN OE; ROMtypeROMROM srambist c4msrom010 Reprin
15、t Copyright 2001 by Chip123 Technology Co., Ltd. All rights reserved ISSN 1609-8633 IC DESIGN MAGAZINE VOLUME 35www.C 7Mar. 2003 = SYNTEST SRAMBIST REPORT FILE = TOOL : srambist V1.1.0 r01 (08/15/00 16:30:26) TIME : Wed Mar 15 08:27:37 2002 OPTIONS SELECTED : NUMBER OF MEMORIES : 1 THE CLOCK BEING USED AS THE BIST CLOCK: Bist Clock Port : CLK BIST CLOCK TRIGGERING : negative t
