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1、Industrial Reference Design Platform I2C Developed by the TSC Americas,Release 1.0,2,IC-bus = Inter-Integrated Circuit bus Bus developed by Philips in the early 80s Simple bi-directional 2-wire bus: serial data (SDA) serial clock (SCL) Has become a worldwide industry standard and used by all major I
2、C manufacturers Multi-master capable bus with arbitration feature Master-Slave communication; two-device only communication (generally) Each IC on the bus is identified by its own address code The slave can operate as a receiver (slave receiver) transmitter (slave transmitter),I2C-Bus Introduction,3
3、,Question: What is wrong with this figure?,I2C-Bus START and STOP Conditions,4,Stop Condition - a LOW to HIGH transition on the SDA line while SCL is HIGH,Start Condition - a HIGH to LOW transition on the SDA line while SCL is HIGH,I2C-Bus START and STOP Conditions,5,Each byte has to be followed by
4、an acknowledge bit,Number of bytes transmitted per transfer is unrestricted,If a slave cant receive or transmit another complete byte of data, it can hold the clock line SCL LOW to force the master into a wait state,During data transfer, SDA must be stable when SCL is High,I2C-Bus Data Transfer,6,Th
5、e I2C specification says: Data transfer with acknowledge is obligatory. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.,A receiver with the address is not present in the I2C bus,The receiver is the
6、master and wants to take control of SDA line again in order to generate a STOP command. The slave transmitter MUST then release the SDA line when it sees the NACK so the master can send the STOP command.,The receiver is performing real-time tasks and it cannot process the received I2C information,Ho
7、wever, there are a few scenarios where there is not an acknowledge (SDA staying HIGH). Which ones?,I2C-Bus Acknowledge and Not Acknowledge,7,I2C-Bus Key Parameters,8,Pull-down transistor required on SDA but not on SCL,I2C-Bus Hardware architecture,9,How do you calculate pull-up resistor values ?,I2C
8、-Bus Pull-up resistors,10,Minimum value There is a minimum resistor value determined by the IC spec limit of 3 mA. R = (Vddmax Volmax)/ 0.003A Example: using a 50.5 V bus: R = (5.5V 0.4V)/ 0.003A = 1.7 k,Maximum value Determined by the IC-bus rise time requirements: V(t1) = 0.3*Vdd = Vdd (11/et1/RC)
9、; then t1 = 0.3566749*RC V(t2) = 0.7*Vdd = Vdd (11/et2/RC); then t2 = 1.2039729*RC t = t2t1 = 0.8472979*RC For standard-mode IC-bus: t = rise time = 1000ns (1 s) so RC = 1180.2 ns Example: at a bus load of 400 pF: Rmax = 2.95 k For fast-mode: IC-bus rise time = 300 ns 400 pF: Rmax = 885 ,I2C-Bus Pul
10、l-up resistor value calculation,11,Each device is addressed individually by software,SCL,c,SDA,I/O,A/D D/A,LCD,RTC,c II,Fixed,Hardware Selectable,1 0 1 0 0 1 1,New devices or functions can be easily “clipped” on to an existing bus!,EEPROM,A0 A1 A2,112 different addresses max with the 7-bit format (o
11、thers reserved),Address allocation coordinated by the I2C-Bus committee,Programmable pins mean that several of the same devices can share the same bus,Unique address per device: fully fixed or with a programmable part through hardware pin(s),10-bit format use a 2 byte message: 1111 0A9A8R/W + A7A6A5
12、A4A3A2A1A0,I2C-Bus Addressing,12,Internal Counters count the Low and High times (TL1, TH1) and (TL2, TH2),TL = longest TL = max (TL1, TL2 ,TLn ) TH = shortest TH = min (TH1, TH2,THn ),Multi Master Mode - Clock Synchronization,13,Two or more masters may generate a START condition at the same time Arb
13、itration is done on SDA while SCL is HIGH - Slaves are not involved,SUMMARY: the master that sends a “1” while the other sends a “0” loses the arbitration,Multi Master Mode - Arbitration,14,to transition on SDA while SCL is HIGH,to transition on SDA while SCL is HIGH,HIGH LOW,LOW HIGH,9 HIGH,LOW,fre
14、e,SDA,lost,master,at the same time,unrestricted,slow down,Test: I2C Protocol Summary,15,IRD IC Functionality,16,PCA9551 8-bit I2C LED Driver,8 open drain LED drivers (on, off, flashing at a programmable rate) with 25 mA driving capability per output 2 selectable, fully programmable blink rates (freq
15、uency and duty cycle) between 0.148 Hz and 38 Hz (6.74 seconds and 0.026 seconds) Input/outputs not used as LED drivers can be used as regular GPIOs Operating power supply voltage range: 2.3 V to 5.5 V Internal oscillator requires no external components Internal power-on reset Active LOW reset input
16、 Edge rate control on outputs Supports hot insertion Low standby current Package offering: SO16 TSSOP16 HVQFN16,17,PCA9551 Device Hardware / Register Definition,18,Registers: INPUT: allows reading of the LED driver outputs PSC0 & PWM0: define the Blinking or Dimming scheme 0 (8-bit value each) PSC1 & PWM1: define the Blinking or Dimming scheme 1 (8-bit value each) LS0 (up to LS3): defin
